Design and power noise cancellation analysis of low dropout voltage regulator

Abstract

Low Dropout (LDO) Voltage Regulator operates with a very small Input Output Voltages with nanometer CMOS technology which enhances density of the chip. Design of Low Dropout voltage Regulators with more execution and less power consuming is a challenging problem. In battery operated devices, hand operated devices and noise sensitive analog devices which need high reliable supply voltages and are battery operated which in turn need Low Dropout Regulators. Now a day the requirement of an LDO is increasing because of more value of portable electronic equipments like cellular phones, camera recorders, pagers, and laptops. This low dropout voltage regulator paper deals with the Design and power noise cancellation Analysis. The simulation of suggested circuit is designed using Tanner EDA tool i.e. Electronic Design Automation tool. The suggested circuit is simulated using 90nm CMOS technology. This proposed LDO gives output voltages in between 0.85V-0.5V from 1V supply voltage. The process parameters and simulation results for 0.85V and 0.5V are presented in this paper.