0.5–1-V, 90–400-mA, Modular, Distributed, 3 × 3 Digital LDOs Based on Event-Driven Control and Domino Sampling and Regulation

Abstract

This article presents on-chip power delivery hardware comprised of nine event-driven (ED) digital low-dropout voltage regulators (LDOs) for a large digital load. The goal is to address the performance degradations in an LDO's accuracy and dynamic load regulation in the presence of parasitics in the power grid of a load. In particular, we investigate the effects of power grid resistance ( R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ), which becomes worse with the size of a digital load and technology scaling. Two critical problems that we address are: 1) the IR drop and 2) the dynamic voltage droop problems. Employing multiple LDOs across the power grid improves the IR drop for mainly better voltage sensing. To tackle the voltage droop problem, we distribute LDOs with ED control such that the LDO closest to a localized droop can instantly correct it. To further improve the feedback control latency, we also enhance each LDO with a novel domino sampling and regulation technique. We prototype the on-chip power delivery system consisting of 3 ×3 digital LDOs in a 65-nm CMOS. We also devise the framework to analyze the stability of the multi-LDO system across R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> values. Measurements show that at 0.5-V (1 V) input, the single LDO exhibits 49.8-mV (94.1 mV) voltage droop for a load current change of 4.04 mA/0.1 ns (13.8 mA/0.2 ns) with a 0.1-nF integrated output capacitor. Also, the nine-LDO system achieves a current density of 248.8 mA/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (1.118.6 A/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) at 0.5-V (1 V) input voltage.