A capacitor-free fast-response low-dropout voltage regulator

A low dropout (LDO) regulator with a wide-bandwidth is proposed in this paper. The regulator features a Human Body Model (HBM) 8kV-class high robustness ElectroStatic Discharge (ESD) protection circuit, and two error amplifiers (one with low gain and wide bandwidth, and the other with high gain and narrow bandwidth). The dual error amplifiers are located within the feedback loop of the LDO regulator, and they selectively amplify the signal according to its ripples. The proposed LDO regulator is more efficient in its regulation process because of its selective amplification according to frequency and bandwidth. Furthermore, the proposed regulator has the same gain as a conventional LDO at 62 dB with a 130 kHz-wide bandwidth, which is approximately 3.5 times that of a conventional LDO. The proposed device presents a fast response with improved load and line regulation characteristics. In addition, to prevent an increase in the area of the circuit, a body-driven fabrication technique was used for the error amplifier and the pass transistor. The proposed LDO regulator has an input voltage range of 2.5 V to 4.5 V, and it provides a load current of 100 mA in an output voltage range of 1.2 V to 4.1 V. In addition, to prevent damage in the Integrated Circuit (IC) as a result of static electricity, the reliability of IC was improved by embedding a self-produced 8 kV-class (Chip level) ESD protection circuit of a P-substrate-Triggered Silicon Controlled Rectifier (PTSCR) type with high robustness characteristics.

This paper presents a capacitor-less low drop-out (LDO) regulator with a slew-rate enhancement circuit. The proposed slew-rate enhancement circuit senses the transient voltage at the output of the LDO to increase the bias current of the error amplifier for a short duration. Hence, the transient response of the regulator is significantly improved due to the enhancement of the slew-rate at the gate of the pass transistor. The proposed LDO regulator has been designed and simulated in UMC 0.18 μm standard CMOS process. Simulation results show that, the LDO regulator consumes a quiescent current of 40 μA only. It regulates the output voltage at 1.2 V from a 1.4 V - 1.8 V supply, with a minimum drop-out voltage of 200 mV at the maximum output current of 100 mA. With the proposed LDO regulator, the amount of overshoot/undershoot in the output voltage under extreme load transients and the settling time of the regulator are 75 mV/ 71 mV and 1.172 μs/ 1.055 μs respectively for a load slew-rate of 99 mA / 1 μs. The proposed LDO regulator has recorded an improvement of 60.9% in terms of the settling time in the post-layout simulation when compared to previously published work.

The external capacitors of conventional LDO (Low Drop Out) regulator have a function to improve the transient response characteristics affected by the overshoot and undershoot. However, the LDO regulator proposed in this study is replaced the function of the external output capacitor with a dual push-pull stage and is achieved a fast transient response by a newly added control path to replace the function of the capacitor removed along with the existing feedback path. The proposed LDO regulator can also be provided the improved ESD (Electro Static Discharge) robustness characteristics by applying the SCR (Silicon Control Rectifier)-based ESD (Electro Static Discharge) protection device embedded into the output node and power line. The LDO regulator with dual push-pull circuit proposed in this study was operated at a maximum load current of 100 mA, an output voltage of 3 V, and an input voltage range of 3.3 ~ 4.5 V. As a result of the measurement, an undershoot voltage of 110 mV and an overshoot voltage of 123 mV were maintained when a load current of 100 mA was applied. Further, the ESD robustness characteristic of HBM is guaranteed at 8kV or higher.

A Nested Miller Compensation with a large feed-forward transconductor for capacitor-less flipped voltage follower low dropout regulator

An active filter-based on-chip DC-DC voltage converter for application to distributed on-chip power supplies in multivoltage systems is described in this paper. No inductor or output capacitor is required in the proposed converter. The area of the voltage converter is therefore significantly less than that of a conventional low-dropout (LDO) regulator. Hence, the proposed circuit is appropriate for point-of-load voltage regulation for noise sensitive portions of an integrated circuit. The performance of the circuit has been verified with Cadence Spectre simulations and fabricated with a commercial 110 nm complimentary metal oxide semiconductor (CMOS) technology. The area of the voltage regulator is 0.015 mm2 and delivers up to 80 mA of output current. The transient response with no output capacitor ranges from 72 to 192 ns. The parameter sensitivity of the active filter is also described. The advantages and disadvantages of the active filter-based, conventional switching, linear, and switched capacitor voltage converters are compared. The proposed circuit is an alternative to classical LDO voltage regulators, providing a means for distributing multiple local power supplies across an integrated circuit while maintaining high current efficiency and fast response time within a small area. Key points: Hybrid regulator, low dropout regulator, on-chip voltage regulation, point-of-load voltage egulation. I. Introduction The power supply voltage aggressively scales with each technology generation, making the delivery of a high quality supply voltage to noise sensitive circuit blocks highly challenging .The number of voltage domains within an integrated circuit is increasing to satisfy stringent power budgets. The increase in the number of voltage domains requires new techniques to generate these voltages close to the load circuitry while occupying a small area. The power savings is greater when the voltage regulators are close to the load devices (point-of-load voltage delivery), and size is therefore the primary issue for point-of-load voltage regulation. Classical power supplies occupy large on-chip area and are therefore not appropriate for point-of-load power delivery. Several topologies are commonly used to generate on-chip dc voltages. These DC-DC voltage converters are generally used as on-chip power supplies in high performance integrated circuits. Conventional DC-DC converters can be grouped into three primary categories: switching, switched capacitor (SC), and linear DC-DC converters . Buck converters, which are step-down switching DC-DC converters, are popular because of their high power efficiency. A second order inductor-capacitor (LC) passive filter is commonly used in a buck converter. The passive LC components require significant on-chip area, therefore, the passive components have generally been implemented offchip. As a consequence of placing these components off-chip, significant voltage drop and bounce are produced at the package level due to the parasitic resistance and inductance between the off-chip components of the voltage converter and the integrated circuit. Additionally, the parasitic interconnect impedance between the discrete components of the voltage converter can produce significant power loss. Furthermore, with power supply scaling, analog and digital circuits are less tolerant to fluctuations in the supply voltage . The parasitic impedance of the interconnect between the discrete components degrades the speed and accuracy of the load regulation, causing slow response times and changing output voltage levels. A more area efficient voltage converter structure is a lowdropout voltage regulator (LDO) . These regulators are implemented on-chip close to the load circuitry for fast and accurate load regulation. These regulators require a large output capacitance to achieve fast load regulation. This capacitor occupies significant on-chip area and is therefore generally implemented off-chip . The off-chip implementation of the output capacitor requires dedicated I/Os and produces higher parasitic losses. Alternatively, when the output capacitor is placed on-chip, the output capacitor dominates the total LDO regulator area . A high bias current of 6 mA is used in to deliver 100 mA current with a 600 pF output capacitor. This approach is not appropriate for low power applications and the output capacitor occupies a significant die area. Many techniques have been proposed to eliminate the need for the large off-chip capacitor without sacrificing the stability and performance

In this paper, a new type of a 90nm CMOS LDO regulator with high load regulation using a gain goost-up technique. The development of low drop-out (LDO) regulator architectures in the power management family is necessary to reduce the standby power of portable applications such as cellular phones and PDAs. In essence, this LDO regulator suffers from an inherent load regulation which impedes to work under various applications. Indeed, this paper discusses a technique that enables the practical realizations of high Load regulation LDO's at low voltages. The objective of this research is to develop novel LDO regulators that can achieve a high precision of LDO which requires a high loop gain performance. Moreover, one of the performances which is enhanced by the augmentation of dc open loop gain is the load regulation. The LDO is implemented in 90 nm CMOS technology and achieves a power-supply rejection ratio better than −70 dB up to 100 KHz for load currents up to 100 mA. The voltage regulator provides maximum 110 mA current, moreover with a 1.2V supply voltage, thus this LDO regulator providing an output of 1 V with a 200mV drop-out voltage.

Low dropout (LDO) regulators are crucial components in power management systems for portable, i.e., battery-powered, devices. However, the design of LDO regulators presents a challenging trade-off between dynamic performance, power consumption, and area efficiency. This paper proposes a novel LDO regulator design that addresses these challenges by employing the reverse nested Miller compensation (RNMC) with current buffers embedded within the own class AB high gain error amplifier (EA) topology, and a time response enhancement circuit (TREC). High-gain (>120 dB) class AB EA renders good regulation performance with enhanced dynamic performance. The proposed compensation scheme improves the gain bandwidth product (GBW) and stability of the regulator, while the TREC reduces overshoot and undershoot during load transients without additional steady-state power consumption. Post-layout simulations confirm the robustness of the proposed 180 nm CMOS design across a wide range of operating conditions, achieving a regulated output voltage of 1.8 V with 100 mV dropout, good load and line regulating performance, and excellent load transient response with reduced undershoot and overshoot at minimum power (Iq = 13.8 μA) and area (314 μm × 150 μm) consumption. The proposed LDO regulator thus offers a compelling compromise between power consumption, area efficiency, and dynamic performance, making it highly suitable for portable applications.

This paper presents an ultra-low-power and high-gain low-dropout (LDO) regulator. It is based on the flipped voltage follower cell with an adaptive biasing technique that is suitable for implantable biomedical applications. The error amplifier for the proposed regulator consists of two cross-coupled common-gate cells and a pseudo-folded-cascode structure to increase the regulator’s loop gain. In addition, three different compensation techniques including Miller, cascode, and Q-reduction are simultaneously utilized at the LDO regulator to achieve high stability despite having the minimum load current and ultra-low power consumption. The proposed LDO regulator has been simulated in TSMC 90-nm CMOS technology with minimum power consumption of 2.8 µW at no load. Post-layout simulation results show that the proposed LDO regulator is stable over load currents from 30 µA to 40 mA with a maximum on-chip CL of 100 pF. Moreover, the voltage regulator settles in less than 850 ns at 0.75 V output voltage that is achieved in response to a load transient step of 40 mA with a rise time of 200 ns. Besides, the obtained line and load regulations are significantly improved to 1 mV/V and 36 µV/mA, respectively.

A capacitor-free CMOS low-dropout (LDO) regulator for system-on-chip (SoC) applications is presented. By adopting AC-boosting and active-feedback frequency compensation (ACB-AFFC), the proposed LDO regulator, which is independent of an off-chip capacitor, provides high closed-loop stability. Moreover, a slew rate enhancement circuit is adopted to increase the slew rate and decrease the output voltage dips when the load current is suddenly switched from low to high. The LDO regulator is designed and fabricated in a 0.6 μm CMOS process. The active silicon area is only 770 × 472 μm2. Experimental results show that the total error of the output voltage due to line variation is less than ±0.197%. The load regulation is only 0.35 mV/mA when the load current changes from 0 to 100 mA.

A wide-load-range low-dropout (LDO) regulator with single-transistor-assisted buffer and analog-digital mixed-mode control is presented in this paper. The single-transistor-assisted PMOS-input unity-gain-buffer can extend the gate voltage range of the analog power transistor and guarantee that the proposed LDO regulator can work well even at very light load current. To extend the loading capability for large load current, a mixed-mode control is used to detect heavy load and turn on or off the digital power transistor which provides large current to the load with better area efficiency. With the digital assistance, the proposed LDO regulator has better load regulation and loading capability at heavy load as well. A proof-of-concept design of the proposed LDO regulator has been implemented and fabricated in a standard $0.18-\mu \mathrm {m}$ CMOS process. It occupies an active area of only $0.01 \mathrm {m}\mathrm {m}^{2}$. With the load current step from 0 mA to 150 mA, the proposed LDO regulator with digital assistance achieves a droop voltage reduction of more than 50% compared to the design without the digital assistance. A load regulation of 0.21 mV/mA is achieved by the proposed design with the help of the digital assistance and single-transistor-assisted buffer.

An on-chip low-dropout (LDO) voltage regulator with a novel technique to improve the settling time and a robust frequency compensation scheme is presented in this paper. The total capacitance required for the utilized compensation topology is only 2.8 pF. The proposed LDO regulator was implemented in a standard 0.35 μm CMOS technology and the simulation results show that the implemented LDO regulator operates from a supply voltage of 2 V to 4 V with a dropout voltage of 200 mV and the maximum load current of 120 mA, consuming 45 μA quiescent (ground) current.

This paper presents the design of low-dropout (LDO) regulator optimized on power efficiency and load transient response. As the LDO is always-on block, the quiescent current is a critical parameter of LDO. The proposed circuit includes an op-amp which shows high slew rate with low quiescent current. A voltage damper circuit is included for fast load transient response. A body feedback loop helps the LDO regulator to react to relatively slow distortion of the output voltage. The proposed LDO regulator is fabricated in a 180 nm CMOS process. The test results show that maximum undershoot is 125.9 mV during load transient and 0.177 ns/$\mu$ m figure-of-merit (FOM) at the quiescent current of 0.02532 mA.

An ultra-low power output-capacitorless low-dropout (LDO) regulator with a slew-rate-enhanced (SRE) circuit is introduced. The increased slew rate is achieved by sensing the transient output voltage of the LDO and then charging (or discharging) the gate capacitor quickly. In addition, a buffer with ultra-low output impedance is presented to improve line and load regulations. This design is fabricated by SMIC 0.18 μm CMOS technology. Experimental results show that, the proposed LDO regulator only consumes an ultra-low quiescent current of 1.2 μA. The output current range is from 10 μA to 200 mA and the corresponding variation of output voltage is less than 40 mV. Moreover, the measured line regulation and load regulation are 15.38 mV/V and 0.4 mV/mA respectively.

This paper presents a transient-improved dynamic-replica low-dropout (LDO) regulator. In the proposed LDO regulator, dynamic-replica and bulk modulation techniques are utilized to significantly improve regulation precision while maintaining good stability over a wide load capacitance range. Furthermore, differentiator-based spike coupling is used to improve the transient responses. A prototype of the proposed LDO is designed and fabricated in a standard 65-nm CMOS process. With 1.2V supply, it achieves 0.2V dropout voltage and supports a maximum of 50mA load current, while allowing for virtually any load capacitance value.

This paper presents a new low-dropout (LDO) regulator with low-quiescent, high-drive and fast-transient performance. This is based on a new composite power transistor composed of a shunt feedback class-AB embedded gain stage and the application of dynamic-biasing schemes to both the error amplifier as well as the composite power transistor. The proposed LDO regulator has been simulated and validated using BSIM3 models and GLOBALFOUNDRIES 0.18-µm CMOS process. The simulation results have shown that the LDO regulator consumes 4.7µA quiescent current at no load, regulating the output at 1V from a minimum 1.2V supply. It is able to deliver up to 450mA load current with a dropout of 200mV. It can be stabilized using a 4.7µF output capacitor with a 0.1Ω ESR resistor. The maximum transient output voltage is 64.6mV on the basis of a load step change of 450mA/10ns under typical condition. The full load transient response is less than 350ns.