Low-dropout Regulator Research Articles

A Successive Approximation Recursive Digital Low-Dropout Voltage Regulator With PD Compensation and Sub-LSB Duty Control

This paper presents a recursive digital low-dropout (RLDO) regulator that improves response time, quiescent power, and load regulation dynamic range over prior digital LDO designs by 1–2 orders of magnitude. The proposed RLDO enables a practical digital replacement to analog LDOs by using an SAR-like binary search algorithm in a coarse loop and a sub-LSB pulse width modulation duty control scheme in a fine loop. A proportional-derivative compensation scheme is employed to ensure stable operation independent of load current, the size of the output decoupling capacitor, and clock frequency. Implemented in 0.0023 mm2 in 65 nm CMOS, the 7-bit RLDO achieves, at a 0.5-V input, a response time of 15.1 ns with a figure of merit of 199.4 ps, along with stable operation across a 20 000 $\times $ dynamic load range.

Low quiescent current capacitorless small gain stages LDO with controlled pass transistors

A low quiescent current 180-nm output-capacitorless low-dropout regulator with small-gain stages (SGSs) is presented in this paper. The proposed technique permits the regulator to distribute the load current into two power transistors depending on the demand of the load using a controller based on load variation criterion. SGSs are introduced to enhance loop gain without low-frequency poles. The proposed architecture does not require compensation capacitor. Thus, the active chip area is reduced to 73.59 µm × 36 µm. The measured results have shown that the fabricated circuit consumes a quiescent current of 1.8 µA at no load, regulating the output at 1 V with maximum output current of 50 mA from a voltage supply of 1.2 V. It achieves full range stability from 0 to 50 mA load current at a maximum 100 pF load capacitor.

Reducing Side-Channel Leakage of Encryption Engines Using Integrated Low-Dropout Voltage Regulators

Low-dropout (LDO) regulators are becoming a part of modern processor architectures for fine-grain power management and higher energy efficiency. This paper shows that these integrated LDOs can also be leveraged to enhance side-channel analysis resistance of encryption engines to power side-channel analysis (PSCA) attacks. The current transformation induced by integrated LDOs coupled with limited bandwidth of the feedback loop help suppress the side-channel leakage. The impact of both analog LDO (ALDO) and all-digital LDO (ADLDO) on the load currents is studied with correlation analysis between the load and the LDO input current. The effectiveness of integrated LDOs as countermeasure to PSCA is further explored with Correlation Power Analysis (CPA) and Test Vector Leakage Assessment (TVLA) performed on both simulated as well as measured load currents for a 128-bit Advanced Encryption Standard (AES) implemented in GF-130-nm process technology. We show that integrated LDOs can enhance PSCA resistance; however, the trade-off between integrated LDO performance and side-channel security is essential. We design integrated LDOs optimized for low-power/compact encryption engines and show that LDO-based protection can increase power attack resistance by >800× with minimal power, area, and performance overheads.

A novel high accuracy bandgap reference voltage source

PurposeThis paper aims to design a new bandgap reference circuit with complementary metal–oxide–semiconductor (CMOS) technology.Design/methodology/approachDifferent from the conventional bandgap reference circuit with operational amplifiers, this design directly connects the two bases of the transistors with both the ends of the resistor. The transistor acts as an amplifier to amplify the change of voltage, which is convenient for the feedback regulation of low dropout regulator (LDO) regulator circuit, at last to realize the temperature control. In addition, introducing the depletion-type metal–oxide–semiconductor transistor and the transistor operating in the saturation region through the connection of the novel circuit structure makes a further improvement on the performance of the whole circuit.FindingsThis design is base on the 0.18?m process of BCD, and the new bandgap reference circuit is verified. The results show that the circuit design not only is simple and novel but also can effectively improve the performance of the circuit. Bandgap voltage reference is an important module in integrated circuits and electronic systems. To improve the stability and performance of the whole circuit, simple structure of the bandgap reference voltage source is essential for a chip.Originality/valueThis paper adopts a new circuit structure, which directly connects the two base voltages of the transistors with the resistor. And the transistor acts as an amplifier to amplify the change of voltage, which is convenient for the feedback regulation of LDO regulator circuit, at last to realize the temperature control.

A Fully Integrated Digital Low-Dropout Regulator Based on Event-Driven Explicit Time-Coding Architecture

This paper presents a fully integrated digital low-dropout (LDO) voltage regulator based on event-driven control architecture. The focus of the paper is to scale the off-chip output capacitor of an LDO conventionally used to compensate fast load current change. To shrink the output capacitor size, it is paramount to shorten control latency. This can be done by employing a high-speed error amplifier in analog LDO designs and by using fast clock in digital synchronous LDO designs. However, those approaches become less suitable for sub-1-V supply voltage due to the headroom problem of analog circuits and/or increase power dissipation due to the high-frequency clock. In this paper, we tackle the tradeoff between power consumption and control latency by introducing an event-driven approach. Our event-driven approach enables to perform regulation tasks only when the output voltage deviates significantly from a set point, simultaneously achieving short latency and low-power dissipation. We prototyped an event-driven digital LDO that supports 400- $\mu \text{A}$ load current at 0.5-V input and 0.45-V output voltage. The measurements show 40-mV droop voltage and 96.3% peak current efficiency with an on-chip integrated 0.4-nF output capacitor.

An External Capacitor-Less Ultralow-Dropout Regulator Using a Loop-Gain Stabilizing Technique for High Power-Supply Rejection Over a Wide Range of Load Current

An external capacitor-less ultra low-dropout (LDO) regulator that can continue to provide high power-supply rejection (PSR) over a wide range of the load current is proposed. Using the loop-gain stabilizer (LGS) to fix the dc level of the output voltage of the error amplifier to the optimal value, the LDO can keep maximizing the unity-gain frequency, while the load current changes widely up to 200 mA. Despite the multiple poles in the regulating loop, the stability can easily be obtained due to an intrinsic left-half plane zero, generated by the auxiliary path of the LGS. The proposed LDO was fabricated in a 40-nm CMOS process, and it had an input voltage of 1.1 V. When the dropout voltage was 0.1 V and the load current was 200 mA, the measured PSRs were −60 and −35 dB at 1 and 10 MHz, respectively. Due to the LGS, the dc loop gain was maintained to be high, resulting in good load and line regulations of $19~\mu {\text{V}}$ /mA and 0.75 mV/V, respectively. While the total current consumption of the LDO was $275~\mu {\text{A}}$ , the LGS consumed only $7~\mu {\text{A}}$ . The area was 0.008 mm2 with 4-pF on-chip capacitance for compensation.

Reduced‐switch SCALDO: an extra low‐frequency DC–DC converter technique for VRM applications

State-of-the-art microprocessors require very low DC-voltages at sub-1 V levels. Many processors draw high-current at low voltages and require low-noise DC-power rails. Switched-mode power supply (SMPS) topologies are the common approach to design voltage regulator modules (VRMs). Fast operations of switches in SMPSs allow the use of smaller inductors but ultimately result in radio frequency and electromagnetic interference issues. Compared to SMPSs, linear regulators have lower noise, high quality DC output, and faster response to the load high-current slew rates; however, with the serious disadvantage of low efficiency. Supercapacitor assisted low-dropout (SCALDO) regulator is a technique to achieve high end-to-end efficiency (ETEE) for linear regulator-based converters. Though, the switch-operation frequency is extremely low, number of switches required for SCALDO configuration is three times larger than that of supercapacitors. Reduced-switch SCALDO (RS-SCALDO) is a topological variation of SCALDO that requires fewer switches. By designing an alternately operated high-current LDO pair, RS-SCALDO can handle high load currents, allowing development of a linear VRM. This study presents a proof of concept prototype of 3.5-to-1.5 V RS-SCALDO for a maximum 5 A load with digitally adjustable output voltages. The prototype achieved an ETEE better than 80%, and required half the switch count of an equivalent SCALDO circuit.

PSR enhancement techniques for output-capacitor-free LDO regulator design

In this paper, power-supply rejection (PSR) enhancement techniques for a output-capacitor-free low drop-out (LDO) regulator with an NMOS pass transistor are presented. For DC PSR and bandwidth enhancement, DC PSR compensation and capacitor cancelation circuits were developed on the basis of precisely derived PSR models of the conventional LDO regulator. The effectiveness of the PSR enhancement techniques were verified using analytic PSR models, SPICE simulation, and measurements. The fabricated LDO regulator using 0.18 \(\upmu\)m CMOS technology maintains PSR less than \(-74\,\hbox {dB}\) up to 10 MHz, while delivering the output current and voltage of 25 mA and 1.2 V, respectively.

Capless LDO Regulator Achieving −76 dB PSR and 96.3 fs FOM

The performance of switching devices such as display driver ICs is degraded by large power supply noise at switching frequencies from a few hundreds of kilohertz to a few megahertz. In order to minimize the power supply noise, a low-dropout (LDO) regulator with higher power supply rejection (PSR) is essential. In this brief, a capless LDO regulator with a negative capacitance circuit and voltage damper is proposed for enhancing PSR and figure of merit (FOM), respectively, in switching devices. The proposed LDO regulator is fabricated in a $0.18~\boldsymbol {\mu }\text{m}$ CMOS. Measurement results show that the proposed LDO regulator achieves −76 dB PSR at 1 MHz and 96.3 fs FOM with a total on-chip capacitance of as small as 12.7 pF.

Multiphysics Performance Evaluation of Flexible Substrate Based 1.2kV SiC Half Bridge Intelligent Power Module with Stacked Dies

Abstract Wide Bandgap (WBG) power devices have become the most promising solution for power conversion systems, with the best trade-off between theoretical characteristics, real commercial availability and maturity of fabrications. Advanced packaging technology is being heavily developed to take full advantages of WBG devices, in terms of materials, mechanical design, fabrication and electrical performance optimizations. In this paper, a flexible substrate based 1.2kV SiC Half Bridge Intelligent Power Module with stacked dies is introduced. The module design is based on the concept “Power Supply in Package (PSiP)”, high functionality is integrated in the module. Together with power stages, gate driver circuits, Low Dropout Regulators (LDO), digital isolators, and bootstrap circuits are integrated in the module. An ultra-thin flexible epoxy-resin based dielectric is applied in the module as substrates, its thickness can be as low as 80μm, with 8W/mK thermal conductivity. The SiC switches are double-side solderable, with copper as topside metallization on pads. No bonding wires are applied in the SiC PSiP module. The highside and lowside SiC switches on the phase leg is stacked vertically for interconnections with low parasitic and high denstiy. This work mainly addresses performance evaluation of the PSiP SiC half bridge module by multiphysics simulations. Q3D is employed to evaluate the parasitic inductance and resistance in the module, showing that parasitic inductance is lower than 1.5nH in the design. The extracted parasitics is imported in spice circuit model, simulation results show limited ringing during switching transients. Thermal simulations are employed to compare junction temperature of power modules with DBC subtrates and flexible substrates, then to evaluate the thermal performance of the designed PSiP SiC model with stacked dies. It shows that junction temperature of designed IPM is higher than regular module at same condition. The paper also provides guideline for optimized heat sink design to lower junction temperature of the SiC IPM. Mechanical simulations are employed to evaluate the pre-stress induced in modules with DBC substrate and flexible dielectric substrate, and proves that mechanical stress induced by reflowing process can be reduced significantly by using ultra-thin flexible dielectric as substrate.

Multiple-Loop Design Technique for High-Performance Low-Dropout Regulator

A new multiple-loop design technique for high-performance low-dropout (LDO) regulator designs has been proposed and successfully implemented in many commercial products for portable smart phone and tablet PC applications. The proposed LDO is composed of five loops that allows designers to obtain a good tradeoff between quiescent current and other performances, such as undershoot, overshoot, and so on. A total of one bandgap reference and 38 LDOs (including n-type and p-type LDOs, which will be named NLDO and PLDO, respectively) were integrated in one power-management IC chip for powering an application processor inside mobile devices. The proposed LDO has been fabricated based on 0.13- $\mu {m}$ CMOS process and supplies various current capacities from 50 to 600 mA; 38 LDOs have been designed and supply different output voltage levels from 0.7 to 3.0 V. One of the proposed NLDOs consumes $14~\mu {A}$ of the quiescent current and features under 56/24 mV of undershoot/overshoot at VOUT =1 V as the load current steps up from 0 to 300 mA with 300 mA/1 $\mu {s}$ on a 1- $\mu {F}$ output capacitor. The measured output load and line regulations are 1.8 and 0.4 mV, respectively. The measured integrated output noise from 10 Hz to 100 kHz at $\text{I}_{\mathrm{ LOAD}}=10\%$ of maximum current shows 80 $\mu {V}$ rms. The package chip size is $6.25 \times 6.25$ mm2 with 169 balls.

Self-Powered RFID Sensor Tag for Fault Diagnosis and Prognosis of Transformer Winding

This paper presents a transformer winding fault diagnosis and prognosis method based on self-powered radio frequency identification (RFID) sensor tag. The proposed RFID sensor tag, which consists of RFID tag, power management circuit, MCU, and accelerometer, can acquire the vibration signals of transformer winding from the tank by accelerometer, and then wirelessly transmit the signals to the RFID reader. An inductive energy harvester utilizing surrounding magnetic field is optimized as power supply for the proposed sensor tag, including the MCU and the accelerometer. A customized ac–dc converter together with a low-dropout voltage regulator is designed to provide stable dc voltage for the proposed sensor tag. The RFID reader compiles the data from all the RFID sensor tags and then transmits them to the remote monitoring software which is developed to display the diagnosis results and alert messages. The experimental results show that the proposed energy harvester can provide 197- $\mu \text{w}$ power in a 50-Hz magnetic field, and the ac–dc converter is capable of providing 2.5-V dc voltage to power the circuitry. The measured maximum power consumption of the proposed sensor tag is 147 $\mu \text{w}$ . Furthermore, the achieved reliable communication distance is 13 m in the test scenario. The experimental results show that the proposed method is effective in term of the diagnosis and prognosis of transformer winding.

Differential CMOS Sub-Terahertz Detector with Subthreshold Amplifier.

We propose a differential-type complementary metal-oxide-semiconductor (CMOS) sub-terahertz (THz) detector with a subthreshold preamplifier. The proposed detector improves the voltage responsivity and effective signal-to-noise ratio (SNR) using the subthreshold preamplifier, which is located between the differential detector device and main amplifier. The overall noise of the detector for the THz imaging system is reduced by the preamplifier because it diminishes the noise contribution of the main amplifier. The subthreshold preamplifier is self-biased by the output DC voltage of the detector core and has a dummy structure that cancels the DC offsets generated by the preamplifier itself. The 200 GHz detector fabricated using 0.25 μm CMOS technology includes a low drop-out regulator, current reference blocks, and an integrated antenna. A voltage responsivity of 2020 kV/W and noise equivalent power of 76 pW/√Hz are achieved using the detector at a gate bias of 0.5 V, respectively. The effective SNR at a 103 Hz chopping frequency is 70.9 dB with a 0.7 W/m2 input signal power density. The dynamic range of the raster-scanned THz image is 44.59 dB.

A Nanosecond-Transient Fine-Grained Digital LDO With Multi-Step Switching Scheme and Asynchronous Adaptive Pipeline Control

This paper introduces a multi-step switching scheme for a digital low dropout regulator (DLDO) that emerges as a new way of achieving nanosecond-transient and fine-grained on-chip voltage regulation. The multi-step switching scheme takes advantage of the adaptive pipeline control and asynchronous clocking for area- and power-efficient digital controller utilization. It speeds up the transient response by varying the pass transistor sizing in two available lengths of coarse steps as per the perturbation, while maintaining a small output voltage ripple by toggling in a finer step at steady operation. A prototype proving the proposed concept, i.e., a 0.6–1.0-V input, 50–200-mV dropout, and 500-mA maximum loading DLDO with an on-chip 1.5-nF output capacitor, is fabricated in a 65-nm CMOS process to verify the effectiveness of this scheme. By employing the multi-step switching scheme and adaptive control, the DLDO achieved a fast transient response to nanoseconds loading current change, and a 100 mV per 10-ns reference voltage switching, as well as a resolution of 768 levels (~9.5 bits) with a 5-mV output ripple. The quiescent current consumed by this DLDO at steady operation is down to $300~{\mu }\text{A}$ .

Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input

This paper proposes a new design for a fast-locked digitally controlled low-dropout regulator (FDLDO) for an ultra-low voltage input. The proposed design involves a fast-locked control mechanism that reduces the settling time of the load transient response in the tracking mode and decreases the quiescent current in the regulating mode. For an ultra-low input voltage of 0.35 V, the proposed FDLDO is capable of providing a regulated output voltage of 0.3 V with a dropout voltage of 50 mV and delivering a maximal load current of 2.4 mA with current and power efficiencies of 99.74 and 85.49%, respectively. Measurement results showed that in the regulating mode, the quiescent current is only 5.15 $$\upmu \hbox {A}$$ for the maximal load current; furthermore, for the maximal load current, the load regulation and the line regulation are 1.5 mV/mA and 4.916 mV/V, respectively. Under the load regulation, the transient response time is less than 15 $$\upmu \hbox {s}$$ . No external output capacitor is required to stabilize the control loop, and there is no external input clock. The proposed FDLDO is suitable for low-power system-on-a-chip applications of wearable electronic devices with an ultra-low supply voltage.

An Output-Capacitorless Ultra-Low Power Low-Dropout Regulator

This paper proposes an output-capacitorless low-dropout (LDO) regulator with ultra-low quiescent power. It applies an adaptive error amplifier to improve the bandwidth and transient response during heavy load, and a second gain stage to improve the stability during light load. Furthermore, an overshoot and undershoot reduction circuit is used to shorten the settling time when output load is changed. The LDO is fabricated in 0.18[Formula: see text][Formula: see text]m CMOS process and occupies a chip area of 0.06[Formula: see text]mm2. The LDO is measured to output a stable voltage at 1.6[Formula: see text]V with a quiescent power of 1.8[Formula: see text][Formula: see text]W. The experimental results also show a good transient response.

A 50-mA 99.2% Peak Current Efficiency, 250-ns Settling Time Digital Low-Dropout Regulator With Transient Enhanced PI Controller

A fully integrated digital low-dropout regulator (DLDO) with a fast transient response, providing a regulated supply for system-on-chip (SoC) power management applications is proposed. Wideband operation and fast transient response are achieved through a transient enhanced proportional-integral controller, without compromising the stability of the DLDO at steady-state operation. The transient enhancement stage boosts loop-gain dynamically during load transients. In the gain boosting mode, the DLDO closed-loop bandwidth is increased, resulting in reduced undershoot/overshoot and fast settling. When the output voltage recovers to the desired level, the boost mode operation is disabled. For a load change with a 4-mA/ns slew rate between 10 and 50 mA, utilizing transient enhancement mode reduced the measured undershoot and overshoot by 35% and 17%, respectively. The characterization results show that the transient enhancement mode can reduce the settling time from 500 to 250 ns for a 10–50-mA load current change. The proposed DLDO operates with an input voltage ranging from 0.84 to 1.24 V, and output voltage ranging from 0.6 to 1 V. The maximum output current of the DLDO is 50 mA and the DLDO achieves a peak current efficiency of 99.2%, with DLDO figure of merit (FOM2) of 63.25 ps. The DLDO prototype chip is fabricated on a 0.13- $\mu \text{m}$ CMOS technology and occupies a 0.0631-mm2 die area.

Fully digital fast transient phase-locked digital LDO-embedded-MDLL for DVFS applications

This paper presents a multiplying delay-locked loop (MDLL) embedded with a frequency-only reference (FREF) based fully digital low-dropout regulator (DLDO) that outperforms conventional dynamic vol...

Fully integrated, low drop-out linear voltage regulator in 180 nm CMOS

This paper presents a capacitor-free low dropout (LDO) linear regulator based on a dual loop topology. The regulator utilizes two feedback loops to satisfy the challenges of hearing aid devices, which include fast transient performance and small voltage spikes under rapid load-current changes. The proposed design works without the need of a decoupling capacitor connected at the output and operates with a 0---100 pF capacitive load. The design has been taped out in a $$0.18\,\upmu \hbox {m}$$0.18μm CMOS process. The proposed regulator has a low component count, area of $$0.012\, \hbox {mm}^2$$0.012mm2 and is suitable for system-on-chip integration. It regulates the output voltage at 0.9 V from a 1.0---1.4 V supply. The measured results for a current step load from 250 to 500 $$\upmu \hbox {A}$$μA with a rise and fall time of $$1.5\,\upmu \hbox {s}$$1.5μs are an overshoot of 26 mV and undershoot of 26 mV with a settling time of $$3.5\,\upmu \hbox {s}$$3.5μs when $${C_L}$$CL between 0 and 100 pF. The proposed LDO regulator consumes a quiescent current of only $$10.5\,\upmu \hbox {A}$$10.5μA. The design is suitable for application with a current step edge time of 1 ns while maintaining $$\Delta V_{out}$$ΔVout of 64 mV.

A Novel Power Management Circuit Using a Super-Capacitor Array for Wireless Powered Capsule Robot

Wireless power transmission (WPT) based on near-field inductive coupling principle is a promising solution to the power supply issue of a freely moving capsule robot (CR) that employs dc motors as actuators. However, the limited inductive power can cause a voltage drop when dc motors start or stall, because short-time peak power is required. To handle the voltage drop issue, we propose the use of a novel power management circuit (PMC) that consists of four successively connected segments of a full-bridge rectifier for ac–dc conversion, a buck dc–dc converter for highly efficient voltage reduction, a power buffer for power storage and short-time power supply, and a low drop-out (LDO) regulator for voltage stabilization. The power buffer is implemented with a super-capacitor array (SCA) that employs the output voltage of the dc–dc converter as its charging voltage. To analyze and optimize the PMC containing the SCA (PMC-SCA), a model is built based on deducing the input resistance relations between each pair of adjacent segments, and its correctness is then validated experimentally. A comparison between the PMC-SCA and the traditional PMC (a rectifier + a regulator) is also conducted, and the former shows superiorities in both reducing voltage drop and improving safety related to temperature rise of onboard receiving coil (RC). Finally, a primary PMC-SCA prototype measuring $\Phi $ 13 mm $ \times $ 4 mm is integrated to an inchworm-like CR for effectiveness validation; the CR working voltage is measured to be higher than 3 V at all times, which ensures the proper functioning of the CR.