Abstract
In this paper, power-supply rejection (PSR) enhancement techniques for a output-capacitor-free low drop-out (LDO) regulator with an NMOS pass transistor are presented. For DC PSR and bandwidth enhancement, DC PSR compensation and capacitor cancelation circuits were developed on the basis of precisely derived PSR models of the conventional LDO regulator. The effectiveness of the PSR enhancement techniques were verified using analytic PSR models, SPICE simulation, and measurements. The fabricated LDO regulator using 0.18 \(\upmu\)m CMOS technology maintains PSR less than \(-74\,\hbox {dB}\) up to 10 MHz, while delivering the output current and voltage of 25 mA and 1.2 V, respectively.
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