Fully integrated, low drop-out linear voltage regulator in 180 nm CMOS

Abstract

This paper presents a capacitor-free low dropout (LDO) linear regulator based on a dual loop topology. The regulator utilizes two feedback loops to satisfy the challenges of hearing aid devices, which include fast transient performance and small voltage spikes under rapid load-current changes. The proposed design works without the need of a decoupling capacitor connected at the output and operates with a 0---100 pF capacitive load. The design has been taped out in a $$0.18\,\upmu \hbox {m}$$0.18μm CMOS process. The proposed regulator has a low component count, area of $$0.012\, \hbox {mm}^2$$0.012mm2 and is suitable for system-on-chip integration. It regulates the output voltage at 0.9 V from a 1.0---1.4 V supply. The measured results for a current step load from 250 to 500 $$\upmu \hbox {A}$$μA with a rise and fall time of $$1.5\,\upmu \hbox {s}$$1.5μs are an overshoot of 26 mV and undershoot of 26 mV with a settling time of $$3.5\,\upmu \hbox {s}$$3.5μs when $${C_L}$$CL between 0 and 100 pF. The proposed LDO regulator consumes a quiescent current of only $$10.5\,\upmu \hbox {A}$$10.5μA. The design is suitable for application with a current step edge time of 1 ns while maintaining $$\Delta V_{out}$$ΔVout of 64 mV.