Capless LDO Regulator Achieving −76 dB PSR and 96.3 fs FOM

Abstract

The performance of switching devices such as display driver ICs is degraded by large power supply noise at switching frequencies from a few hundreds of kilohertz to a few megahertz. In order to minimize the power supply noise, a low-dropout (LDO) regulator with higher power supply rejection (PSR) is essential. In this brief, a capless LDO regulator with a negative capacitance circuit and voltage damper is proposed for enhancing PSR and figure of merit (FOM), respectively, in switching devices. The proposed LDO regulator is fabricated in a $0.18~\boldsymbol {\mu }\text{m}$ CMOS. Measurement results show that the proposed LDO regulator achieves −76 dB PSR at 1 MHz and 96.3 fs FOM with a total on-chip capacitance of as small as 12.7 pF.