Loop Filter Research Articles

Performance improvement of fractional N-PLL synthesizers for digital communication applications

Loop filter with two order was designed to improve the performance of the fractional N-phase locked loop (PLL) circuit (reference spurs noise and switching time), decreasing these two factors give good characteristic to fractional N-PLL circuit, the second order and third order loop filters are widely used in frequency synthesizer because they give good stability tolerance and for their simple architecture. They are designed at bandwidth B=125 KHz and its multipoles, at two values of the phase margin (pm)= 35°, 57°. MATLAB program was used to find the lock time, the component values for each element in the loop filter, also the filter impedance T(s), the bode plot of frequency response for close loop (CL) and open loop gain (OL). It is found by comparing the result of the frequency response for the 2 nd order loop filter and 3 rd order loop filter, that increasing the order of the filter will reduce the spurs noise that destroy the received signal at receiving side.

Stabilization of the backward wave oscillator frequency for operation with high quality resonators

This article describes the performance of a backward wave oscillator, stabilized with phase locked loop. The backward wave oscillator is locked to the frequency of a direct digital synthesizer using an automatic phase locked loop. The direct digital synthesizer is playing the role of tuning part in the suggested frequency synthesizer. Mathematical evaluations of the stability, phase noise and locking speed of the suggested frequency synthesizer are obtained. The optimization technique of frequency synthesizers parameters is presented. This allows to get the maximum response speed and the lowest phase noise and level of spurious with fine tuning (less than 1 Hz). It was shown that the order and type of loop filter in the frequency synthesizer will affect simultaneously the response speed, phase noise and spurious level. The results of this paper shows that the frequency synthesizer can be used in small samples properties measurement using open resonators.

A 13.8-ENOB Fully Dynamic Third-Order Noise-Shaping SAR ADC in a Single-Amplifier EF-CIFF Structure With Hardware-Reusing kT/C Noise Cancellation

To design noise-shaping successive approximation register (NS-SAR) analog-to-digital converters (ADCs) with high resolution and good power efficiency, two key bottlenecks need to be addressed. One is to realize a high-order loop filter with low circuit overhead, and the other is to mitigate the thermal noise. This article presents an NS-SAR ADC that synergistically addresses both challenges. To achieve high-order efficiency, it proposes an innovative error feedback-cascaded integrator feedforward (EF-CIFF) structure that realizes third-order noise shaping using only a single amplifier. It combines the merits of both structures, showing improved robustness, and is free of dc offset concern. On reducing the kT/C noise, this work features a sampling kT/C noise cancellation (SNC) technique that reuses the native hardware of the EF-CIFF structure. An open-loop self-quenching floating-inverter dynamic amplifier (FIDA) is used to support all amplification with low noise and power. Prototyped in 65-nm CMOS, this work achieves 84.8-dB signal-to-noise-distortion ratio (SNDR) with 625-kHz bandwidth (BW) (OSR = 8) and 119 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> , leading to 182-dB Schreier Figure of Merit (FoM). It uses only 0.8-pF input capacitance, which is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5\times $ </tex-math></inline-formula> smaller than prior NS-SAR ADCs with similar oversampling ratio (OSR) and SNDR.

Design and Implementation of High Frequency and Low-Power Phase-locked Loop

Phase-locked loop (PLL) operates at a high frequency and due to the increased switching rate of the circuits, the power consumption is high. Designing a PLL which consumes less power without compromising the frequency of operation is essential. The sub-components of PLL such as the phase frequency detector, charge pump, loop filter, voltage-controlled oscillator, and the frequency divider have to be designed for reduced power consumption. The proposed PLL along with its sub-components have been designed using the CMOS 180nm technology library in the Cadence Virtuoso and simulated using Cadence Spectre with a supply voltage of 1.8V resulting in a 20% reduction in power with a higher frequency of operation compared to the reference PLL architecture. The capture range and lock range of the proposed PLL are 2.09 to 2.14 GHz and 1 to 3.5GHz, respectively. The designed PLL consumes less power and operates at a higher frequency.

Online harmonic extraction and synchronization algorithm based control for unified power quality conditioner for microgrid systems

This manuscript proposes an Adaptive Linear Neural Network (ADALINE) based control for the unified power quality conditioner to protect the critical loads from voltage related power quality problems and mitigate the current related power quality problems produced by nonlinear loads. Due to parallel computing feature and simple algorithm, ADALINE is utilized widely in parameter estimation. In this manuscript, unified ADALINEs based current harmonic extractor for the shunt active power filter is utilized, and an ADALINE based control technique is utilized to produce reference voltages for load voltage compensation. Due to ADALINE control, the necessity of a phase locked loop and conventional filters are omitted, therefore, enabling the system to extract the fundamental components more accurately. Besides, the ability of self-regulating transition from islanded mode to grid-connected mode has ensured that uninterrupted power supply is provided to the critical loads. The system performance is validated through simulation results utilizing MATLAB-Simulink software considering several dynamic conditions, namely unbalanced grid voltage, self-regulating transition, and grid unavailability.

A Resilient FLL Control for Solar-Hydro Generation Based Utility Interactive Microgrid With Enhanced Power Quality

This article focuses on the control based on an extended second-order generalized integrator with a frequency locked loop (Ext-SOGI-FLL) to provide satisfactory performance for synchronization of microgrid (MG). In the existing phase-locked loop (PLL) based control, the loop filter used is not capable to entirely remove harmonics. Hence, the harmonics in voltage considerably affect the frequency as well as phase extraction, both in the dynamics and steady-state situations. To deal with this problem in this system, the voltage source converter is controlled using Ext-SOGI-FLL. This control algorithm extracts the fundamental voltage and current for assessment of phase angle and reference source current (maintaining the required IEEE power quality standard-519 & 1547). This FLL-based control is also capable of estimating the exact frequency and phase magnitude, which suffer from phase offset due to frequency change. The comparative results validate that the response of Ext-SOGI-FLL control in comparison to the existing control algorithms is faster at loads and generation perturbations. Simulated and test results for MG system combining a solar photovoltaic, pico-hydropower generation, and battery validate its performance while feeding local loads uninterruptedly.

A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping

Noise-shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) using passive loop filters have drawn the increasing attentions owing to their simplicity, low power, zero static current, and PVT robustness. However, prior works show the limited resolution because of two main challenges: the thermal noise and the digital-to-analog converter (DAC) mismatch. This article presents a high-resolution full passive NS SAR ADC. It uses an efficient NS filter architecture that realizes a 4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> passive gain and the passive summation, significantly reducing the total thermal noise. It also realizes the second-order DAC mismatch error shaping (MES) that is tone-free. A digital prediction is proposed to solve the signal-range loss issue caused by the MES, recovering the ADC input signal range to the full swing. A prototype NS SAR ADC is implemented in 40-nm CMOS process. It measures 90.5-dB signal-to-noise-and-distortion ratio (SNDR) and 94.3-dB dynamic range (DR) over 40-kHz bandwidth without any calibration. It consumes 67.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> power from a 1.1-V supply and occupies 0.061 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area.

A 2.3 GHz 2.8 mW Sampling ΔΣ PLL Achieving −110 dBc/Hz In-Band Phase Noise and 500 MHz FMCW Chirp

A phase interpolator (PI)-free fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> sampling phase-locked loop (SPLL) has been proposed and implemented in 130 nm CMOS technology, which eliminates time-domain PI, digital-to-time converter (DTC), or background calibration. This phase-locked loop (PLL) employs two linear slope generators (LSGs) to produce linear waveforms, which are related to the VCO feedback phase. Then the reference directly samples the LSG outputs to obtain the phase error. Following this, a 3 bit DAC-based phase interpolating charge pump (PICP) is utilized to interpolate the phase error before feeding it to the loop filter. This enables the SPLL to achieve a fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> ratio without any DTC or calibration. On-chip frequency-modulated continuous-wave (FMCW) chirp generation is also included, which provides 500 MHz FMCW chirp with reconfigurable chirp rate and up to 25% chirp bandwidth to carrier frequency ratio. It consumes 2.8 mW from a 1.2 V supply and occupies an active area of about 0.4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . With a 50 MHz crystal reference, the in-band phase noise is measured to be 109 dBc/Hz at 200 kHz offset. The FoM for the system is measured as −243~ −247.5 dB.

A novel system-level modeling and design approach for high performance single-loop sigma-delta (∑Δ) modulators

PurposeThis paper attempted a novel approach for system-level modeling and simulation of sigma-delta modulator for low-frequency CMOS integrated analog to digital interfaces. Comparative analysis of various architectures topologies, circuit implementation techniques are described with analytical procedure for effective selection of topologies for targeted specifications.Design/methodology/approachVirtual instruments are presented in labview environment to analyze the correlation of circuit-level non-ideal effects with key design parameters over sampling ratio, coarse quantizer bits and loop filter order. A fourth-order single-loop sigma-delta modulator is designed and verified in MATLAB simulink environment with careful selection of integrator weights to meet stable desired performance.FindingsThe proposed designed achieved SNDR of 122 dB and 20 bit resolution satisfying high-resolution requirements of low-frequency biomedical signal processing applications. Even though the simulation performed at behavioral level, the results obtained are considered as accurate, by including all non-ideal and non-linear circuit errors in simulation process.Originality/valueVirtual instruments using labview environment used to analyze the correlation of circuit-level non-ideal effects with key design parameters over sampling ratio, coarse quantizer bits and loop filter order for accurate design.

Abnormal Noise Suppression and Detail Protection for High-Resolution Range Profile of GM-APD Lidar

The noise suppression of high-resolution range profile (HRRP) is a prerequisite for Geiger-mode of avalanche photodiodes (GM-APD) lidar to achieve precise sensing. However, it is difficult to balance the suppression effect and the integrity of detailed information. Considering this problem, we propose a Bayesian network-based improved loop filter (BNILF) for abnormal noise suppression. Based on the ILF, the Bayesian non-average local filtering model is established to calculate a distance of Pearson distance, which gives the criterion of noise judgment. Furthermore, the block preselection is used to accelerate identify abnormal noise and complete range profile noise suppression. To evaluate the performance of this algorithm, simulation and physical system experiments are carried out. The results show that the proposed algorithm has a better noise suppression effect and a higher detailed information protection ability in comparison with the existing typical approaches.

VVC In-Loop Filters

This paper presents an overview of the technologies for in-loop processing and filtering in the Versatile Video Coding (VVC) standard. These processes comprise luma mapping with chroma scaling, deblocking filter, sample adaptive offset, adaptive loop filter and cross-component adaptive loop filter. They are qualified as “in-loop” because they are applied inside the encoding and decoding loops, before storing the pictures in the decoded picture buffer. The filters are complementary and address different purposes. Luma mapping with chroma scaling aims at adaptively modifying the coded samples distribution for improved coding efficiency. The deblocking filter aims at reducing blocking discontinuities. Sample adaptive offset mostly aims at reducing artifacts resulting from the quantization of transform coefficients. Adaptive loop filter and cross-component adaptive loop filter are adaptive filters enabling to enhance the reconstructed signal, using for instance Wiener-filter encoding approaches. The paper provides an overview of the in-loop filtering process and a detailed description of the filtering algorithms. Objective compression efficiency results are provided for each filter, with indication of cumulative coding gains. Subjective benefits are illustrated. Implementation issues considered during the design of the VVC in-loop filters are also discussed.

Sensorless Control Strategy for BLDC Motors Based on a Type-3 Phase Locked Loop

This paper presents the design procedure of a high-performance sensorless control strategy for the widely used brushless DC (BLDC) motors. Generally, conventional sensorless techniques are based on detecting the zero-crossing instants (ZCP) of the back electromotives forces (back-EMFs) of the three phases. These methods, although widely adopted and marketed on an industrial level, involve many limitations such as filtering delays, difficulty to operate at low speeds and immunity against Electromagnetic Interferences (EMI). In this paper, the main objective is to develop a sensorless control technique integrally independent from the zero-crossing points of the back-EMFs. In the proposed method, a zero-delay adaptive filter was used to extract the fundamental and the quadrature components of the line-to-line voltage of the motor. Then, the Synchronous Reference Frame Phase Locked Loop (SRF-PLL) is used to estimate the electrical angle of phase-to-phase back-EMF along with the rotor speed. The conventional SRF-PLL was implemented using a second-order loop filter (type-3 PLL) in order to improve synchronization performances and for better rejection of voltage spikes induced in motor phases during commutations. The benefits of the control technique are brought to light through simulation results. An experimental prototype was designed to confirm the validity of the proposed method.

A Fully Dynamic Low-Power Wideband Time-Interleaved Noise-Shaping SAR ADC

This article proposes a fully dynamic, low-power, wideband, time-interleaved (TI), noise-shaping (NS) successive-approximation-register (SAR) analog-to-digital converter (ADC) based on the cascade of integrators with feedforward (CIFF) architecture. Both the interleaving operation and the loop filter are implemented by using the fully passive switched-capacitor circuits. The feedforward summation is realized by a multi-path dynamic comparator. The overall noise transfer function (NTF) is highly robust against process, voltage, and temperature (PVT) variations since the NTF is determined by device ratios. This allows the NTF zeros to be close to 1, with a good NS effect. Compared with a recently published TI NS SAR based on the error-feedback (EF) architecture, this work does not need a static amplifier, thus leading to the fully dynamic operation. Meanwhile, it eliminates the dependence of NTF on the PVT-sensitive amplifier gain. Implemented in a 40-nm CMOS process, the prototype ADC achieves an SNDR of 69.1 dB, a bandwidth of 50 MHz, and a power consumption of 8.5 mW under a 1.1-V supply, leading to a Walden FoM of 36.3 fJ/conv.-step.

Integer N Synthesizer Design for LoRa Transceivers

This paper presents the study and design of an Integer N synthesizer model for three LoRa ISM bands: 430 MHz 868 MHz and 915 MHz. The proposed topology is composed by two voltage controlled oscillators working in two different bands. The presented model uses the same phase-frequency detector, charge pump and loop filter. This study is focused on dynamic and steady-state analysis in order to infer the synthesizer stability and bandwidth. The performed study shows that the settling time for all bands is less than 40 µs for a bandwidth of 102 kHz.

Low Power, Wide Range Synthesizer for 534 MHz–18.56 GHz Band with FoM of − 192.45 dBc/Hz

A wide range frequency synthesizer is designed with the help of dual voltage tunable Differential Ring Oscillator (DRO). Frequency ranging from 534[Formula: see text]MHz to 18.56[Formula: see text]GHz can be generated using the proposed synthesizer. As proposed circuit utilizes dual voltage tunable DRO, a select input is provided to control the output frequency range. Logic low value (0[Formula: see text]V) of select input generates frequencies from 534[Formula: see text]MHz to 5.08[Formula: see text]GHz whereas logic high value (1.1[Formula: see text]V) of select input enables the frequency generation in the range of 5.08[Formula: see text]GHz to 18.56[Formula: see text]GHz. This work utilizes a single charge pump and single loop filter along with charge pump and bias control circuit. Proposed circuit is designed in GPDK 45-nm CMOS technology with supply voltage of 1.1[Formula: see text]V. Power consumption of the proposed circuits is 2.88[Formula: see text]mW while generating frequency of 7.84[Formula: see text]GHz. Proposed synthesizer demonstrates Figure of Merit (FoM2) of [Formula: see text][Formula: see text]dBc/Hz at this frequency. Because of such a wide spectrum, this synthesizer is well suited in the field of satellite communication, GPS and navigation.

A Pipelined Noise-Shaping SAR ADC Using Ring Amplifier

In this study, a pipelined noise-shaping successive-approximation register analog-to-digital converter (PLNS-SAR ADC) structure was proposed to achieve high resolution and to be free from comparator design requirements. The inter-stage amplifier and integrator of the PLNS-SAR ADC were implemented through a ring amplifier with high gain and speed. The ring amplifier was designed to improve power efficiency and be tolerant to process–voltage–temperature (PVT) variation, and uses a single loop common-mode feedback (CMFB) circuit. By processing residual signals with a single ring amplifier, power efficiency can be maximized, and a low-power system with 30% lower power consumption than that of a conventional PLNS-SAR ADC is implemented. With a high-gain ring amplifier, noise leakage is greatly suppressed, and a structure can be implemented that is tolerant of mismatches between the analog loop and digital correction filters. The measured signal to noise distortion ratio (SNDR) is 70 dB for a 5.15 MHz bandwidth (BW) at a 72 MS/s sampling rate (Fs) with an oversampling ratio (OSR) of 7, and the power consumption is 2.4 mW. The FoMS,SNDR (= SNDR + 10log10BW/Power) is 163.5 dB. The proposed structure in this study can achieve high resolution and wide BW with good power efficiency, without a filter calibration process, through the use of a ring amplifier in the PLNS-SAR ADC.

A Capacitively Coupled CT Δ ΣM With Chopping Artifacts Rejection for Sensor Readout ICs

This paper presents a sensor readout integrated circuit (ROIC) using a capacitively coupled instrumentation amplifier (CCIA)-embedded continuous-time ΔΣ modulator (CT ΔΣM) incorporating chopping artifact rejection. Chopping is an essential technique for suppressing the offset and 1/f noise. However, the chopping artifacts in the modulator loop degrade the in-band noise, linearity, and loop stability. In the proposed design, chopping aliasing is avoided by setting the chopping frequency ( f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch</sub> ) same as the sampling frequency ( f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> ). The chopping ripple is mitigated using the ripple reduction loop (RRL), and the shaped quantization noise-folding resulting from the RRL is prevented by minimizing the loop gain and bandwidth of the RRL. The residual ripple and spikes are filtered out using the alias rejection band of CT ΔΣM. The third-order loop filter enables sufficient noise-shaping with a low oversampling ratio (OSR). The chip is implemented in a 180-nm CMOS process with an active area of 1.65 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , drawing 232.2 μA at a 1.8 V supply. The proposed capacitively coupled (CC)-CT ΔΣM has a 19.4 nV/ √{Hz} input-referred noise density, 1.9 μV offset, 0.08% gain error, 16 ppm integral nonlinearity (INL), and 140 dB common-mode rejection ratio (CMRR) within an input range of 60 mV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> . With -110.1 dB total harmonic distortion (THD), excellent dynamic linearity performance is achieved owing to the CCIA-integrated design and chopping artifact rejection technique.

PLL-based nanoresonator driving IC with automatic parasitic capacitance cancellation and automatic gain control

This paper presents a phase-locked loop (PLL) based resonator driving integrated circuit (IC) with automatic parasitic capacitance cancellation and automatic gain control. The PLL consisting of a phase frequency detector (PFD), a loop filter, and a voltage-controlled oscillator (VCO) makes the driving frequency to be locked at the resonant frequency. The resonator is modeled by Butterworth–Van Dyke equivalent circuit model with motional resistance of 72.8 kΩ, capacitance of 6.19 fF, inductance of 79.4 mH, and parasitic parallel capacitance of 2.59 pF. To mitigate the magnitude and phase distortion in the resonator frequency response, it is necessary to compensate for the parasitic capacitance. The proposed automatic parasitic capacitance cancellation loop is operated in the open-loop mode. In the automatic parasitic capacitance cancellation phase, the outputs of the transimpedance amplifier (TIA) at the lower and higher frequency than the resonant frequency (VH and VL), are compared, and the programmable compensation capacitor array matches the VH and VL using binary-searched algorithm to cancel the parallel parasitic capacitance. The automatic gain control (AGC) loop keeps the oscillation at the suitable amplitude, and the AGC output can be used as a measurement of the motional resistance. The AGC loop is also digitally controlled. The proposed resonator driving IC is designed in a 0.18-μm bipolar complementary metal oxide semiconductor double-diffused metal oxide semiconductor (BCDMOS) process with an active area of 3.2 mm2. The simulated phase noise is −61.1 dBc/Hz at 1 kHz and the quality factor ( Q-factor) is 59,590.

A Multi-Step Incremental Analog-to-Digital Converter With a Single Opamp and Two- Capacitor SAR Extended Counting

This work describes a hybrid incremental ADC (IADC) with two-capacitor (2-C) successive-approximation registers (SAR) extended counting in two-step operation to achieve high resolution data conversion. The circuits in the first step is acting as a first-order incremental analog-to-digital converter (IADC). Finite impulse response (FIR) DAC is incorporated in the loop filter to reduce the transient voltage step. It is reconfigured as a 2-C SAR to perform extended counting technique in the second step. Only one opamp is re-used in both steps. The hardware is prototyped in 0.18 μm CMOS technology, and the hybrid ADC accomplishes a measured DR / SNR / SNDR of 100.2 / 97.1 / 96.6 dB and an input signal bandwidth of 1.2 kHz. Operated at 1.5-V, it consumes 33.2 μW, and this achieves a Walden figure-of-merit (FoM) of 0.25 pJ/conversion-step and Schreier FoM of 175.8 dB.

Auto-Zeroing Static Phase Offset in DLLs Using a Digitally Programmable Sensing Circuit

This brief presents a static phase offset (SPO) reduction technique through auto-zeroing in a delay-locked loop (DLL). We propose a self-calibrated, digitally programmable, sensing circuit that can measure both the polarity and the magnitude of the SPO. The SPO is suppressed by tuning a pair of digital-to-time converters (DTCs) at the input of the phase frequency detector (PFD). The proposed technique enables run-time background calibration and can suppress the SPO caused by artifacts from the PFD, charge pump, and loop filter capacitor. Monte Carlo simulation results show that the SPO in a conventional DLL implementation improves from 12.92 ps to 0.90 ps when the proposed auto-zeroing technique is employed.