Abstract
In this study, a pipelined noise-shaping successive-approximation register analog-to-digital converter (PLNS-SAR ADC) structure was proposed to achieve high resolution and to be free from comparator design requirements. The inter-stage amplifier and integrator of the PLNS-SAR ADC were implemented through a ring amplifier with high gain and speed. The ring amplifier was designed to improve power efficiency and be tolerant to process–voltage–temperature (PVT) variation, and uses a single loop common-mode feedback (CMFB) circuit. By processing residual signals with a single ring amplifier, power efficiency can be maximized, and a low-power system with 30% lower power consumption than that of a conventional PLNS-SAR ADC is implemented. With a high-gain ring amplifier, noise leakage is greatly suppressed, and a structure can be implemented that is tolerant of mismatches between the analog loop and digital correction filters. The measured signal to noise distortion ratio (SNDR) is 70 dB for a 5.15 MHz bandwidth (BW) at a 72 MS/s sampling rate (Fs) with an oversampling ratio (OSR) of 7, and the power consumption is 2.4 mW. The FoMS,SNDR (= SNDR + 10log10BW/Power) is 163.5 dB. The proposed structure in this study can achieve high resolution and wide BW with good power efficiency, without a filter calibration process, through the use of a ring amplifier in the PLNS-SAR ADC.
Highlights
Academic Editors: Kamal El-Sankary and Karama M
There have been continuing attempts to develop analog-to-digital converter (ADC) that can minimize power consumption while possessing a structure optimized for complementary metal-oxidesemiconductor (CMOS) process scaling [1,2]
It consists of a 1st stage for quantizing the most significant bits (MSBs), 2nd stage for quantizing the least significant bits (LSBs), and inter-stage amplifier for amplifying the residual voltage of the 1st stage
Summary
Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations. It consists of a 1st stage for quantizing the most significant bits (MSBs), 2nd stage for quantizing the least significant bits (LSBs), and inter-stage amplifier for amplifying the residual voltage of the 1st stage. The 1st stage quantization noise (Q1 ) and comparator noise (NCMP1 ) can be be attenuated by 1/G the can pipeline structure, by so high filter, and through. ADC (PLNS-SAR ADC) that can improve speed and power efficiency using a ring amplifier, achieving high resolution by applying noise-shaping at each pipeline stage. This paper is organized as follows: Section 2 displays the architecture of this work, Section 3 describes circuit implementation, Section 4 presents the measurement results, and Section 5 presents the conclusion
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