Design and Implementation of High Frequency and Low-Power Phase-locked Loop

Premananda B S,Vaishnavi S Parashar,D Aneesh Bharadwaj,Dhanush T N

doi:10.24840/2183-6493_007.004_0006

Abstract

Phase-locked loop (PLL) operates at a high frequency and due to the increased switching rate of the circuits, the power consumption is high. Designing a PLL which consumes less power without compromising the frequency of operation is essential. The sub-components of PLL such as the phase frequency detector, charge pump, loop filter, voltage-controlled oscillator, and the frequency divider have to be designed for reduced power consumption. The proposed PLL along with its sub-components have been designed using the CMOS 180nm technology library in the Cadence Virtuoso and simulated using Cadence Spectre with a supply voltage of 1.8V resulting in a 20% reduction in power with a higher frequency of operation compared to the reference PLL architecture. The capture range and lock range of the proposed PLL are 2.09 to 2.14 GHz and 1 to 3.5GHz, respectively. The designed PLL consumes less power and operates at a higher frequency.

Highlights

A communication system with low power consumption, higher performance and reduced jitter is considered highly efficient
Simulation results of the phase frequency detector The simulation of the Phase Frequency Detector (PFD) circuits is performed in the frequency range of 100 kHz to 4 GHz with a supply voltage, set at 1.8 V
A design and implementation of the power efficient Phase-locked loop (PLL) architecture is proposed in order to increase the power efficiency and reduce area

Summary

Introduction

A communication system with low power consumption, higher performance and reduced jitter is considered highly efficient. A Phase-locked loop (PLL) can track an input frequency, synchronize signals and generate a frequency that is a multiple of the input frequency (Kaipu et al 2016; Ravisaheb and Nagpara 2017). The components- Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LF), Voltage Controlled Oscillator (VCO) and the frequency divider (Divide by N counter) are integrated to form the mainframe of the PLL system. The phase difference that exists between the two input signals is proportional to the output produced by the PFD. A minimum phase error can be achieved by producing a DC voltage that controls the VCO. The charge pump circuit is used to combine the two outputs of the PFD into a single output, which is fed into the input of the loop filter (Praseetha, Benedict Tephila, and Anusuya 2019)

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