Loop Filter Design Research Articles

Optimal loop filter design of a DC immunity single-phase PLL based single delay operator

Optimal loop filter design of a DC immunity single-phase PLL based single delay operator

A High Dynamic Velocity Locked Loop for the Carrier Tracking of a Wide-Band Hybrid Direct Sequence/Frequency Hopping Spread-Spectrum Signal

For hybrid direct sequence/frequency hopping (DS/FH) spread spectrum signals, even if the relative motion speed between the transmitter and receiver remains constant, the Doppler frequency will vary due to the continuous hopping of the carrier frequency. Under high dynamic conditions, the first-order and second-order change rates of the Doppler frequency attached to the received signal further increase the Doppler frequency agility, making it difficult for the carrier tracking loop to maintain steady-state tracking. To address these issues, a high dynamic velocity locked loop (HD-VLL) is proposed in this paper. Specifically, the accumulated phase tracking error caused by acceleration and jerk is first analyzed. Subsequently, to compensate for this phase tracking error with the system clock, the proposed loop adds an acceleration compensation module and a jerk compensation module. However, this results in the output of the high dynamic loop filter being updated with the system clock, which contradicts the multiplexing design of a traditional loop filter for parallel signal processing, making the hardware implementation of an HD-VLL impractical. Therefore, this contradiction leads us to design an HD-VLL-based multi-carrier NCO (HD-VLL-NCO). The HD-VLL and HD-VLL-NCO are simulated, revealing the HD-VLL’s superior dynamic adaptability and steady-state tracking, while the HD-VLL-NCO achieves comparable accuracy with the appropriate truncation bit width.

Advanced Single-Phase PLL-Based Transfer Delay Operators: A Comprehensive Review and Optimal Loop Filter Design

In recent years, several research works have addressed and developed the phase-locked loop (PLL) in single-phase grid-connected converters with different structures and properties. Each has merits and demerits, such as a complex structure, high computational burden, and slow transient response. This paper aims to comprehensively review advanced single-phase PLLs based on transport delay operators to realize signal orthogonality. A deep insight into the PLLs’ small-signal modeling, main characteristics, stability analysis, and loop filter design are provided in this paper. The main advantages and drawbacks are explained for each type of PLL in terms of different performance indexes, such as settling time, estimation error, and ripples in the estimated grid information. This paper also aims to provide optimal tuning and design of the loop filter gains from the large-signal model point of view, including all the nonlinearities, adopting the stochastic optimization method. All simulations are implemented using the MATLAB/Simulink 2018b environment to validate all theoretical analyses of this paper. The sampling and nominal frequencies are set to be 100 kHz and 50 Hz throughout all the simulation studies.

A Phase-Locked Loop With Inherent DC Offset Rejection for Single-Phase Applications

In this article, we aim to design a simple dc immune phase-locked loop (PLL) for single-phase applications. The dc offset is inherently rejected using only two delay operators. The dc offset in the synchronization unit is a challenging problem that causes oscillation in the estimated grid information. Using conventional filters to solve this problem is ineffective since this degrades the synchronization unit's dynamic performance. Different PLLs have been introduced in this article to mitigate the dc offset. Each has its merits and demerits, such as complex structure, high computational burden, and slow transient response. The proposed PLL incorporates two cascaded delayed signal cancellation operators with an arbitrary-length time delay, rejects the dc offset, and perfectly synchronizes with the grid. This article also presents a small-signal model to facilitate the loop filter design and stability analysis. Besides the simulations, the PLL's performance is validated experimentally under various disturbance conditions, with comparisons with other PLLs.

Quasi Type-1 PLL With Tunable Phase Detector for Unbalanced and Distorted Three-Phase Grid

Out of various moving average filter (MAF)-based phase-locked-loop (PLL), quasi type-1 PLL (QT1-PLL) is widely adopted due to its fast dynamic performance, implementation simplicity, and harmonics rejection abilities. However, the performance of QT1-PLL deteriorates in the presence of an off-nominal frequency unbalanced grid voltage component. Moreover, the sensitivity towards the fundamental frequency negative sequence (FFNS) component is high. Hence, this paper proposes a novel enhanced QT1-PLL solution that is insensitive to unbalance in the grid voltage signal during off-nominal frequency conditions. The proposed adaptive phase detector makes it possible to estimate both the fundamental frequency positive sequence (FFPS) and FFNS components with a high degree of immunity against harmonics. Notably, the pre-loop separation of the FFPS and the FFNS components helps suppress the second harmonic oscillations for improving the parameter estimation accuracy. The loop-filter design of QT1-PLL remains unaffected and requires a proportional gain to estimate the fundamental phase and frequency information. To address the DC offset issue, a modified delayed signal cancellation method is also proposed, which can theoretically eliminate the DC offset for any arbitrary delay length. A small-signal model of the proposed PLL is developed for the sake of stability analysis. Comparative numerical simulation and experimental results are provided with various variants of QT1-PLLs to demonstrate the performance improvement achieved with the proposed technique.

Bandwidth correction of Swarm GPS carrier phase observations for improved orbit and gravity field determination

Gravity fields derived from GPS tracking of the three Swarm satellites have shown artifacts near the geomagnetic equator, where the carrier phase tracking on the L2 frequency is unable to follow rapid ionospheric path delay changes due to a limited tracking loop bandwidth of only 0.25 Hz in the early years of the mission. Based on the knowledge of the loop filter design, an analytical approach is developed to recover the original L2 signal from the observed carrier phase through inversion of the loop transfer function. Precise orbit determination and gravity field solutions are used to assess the quality of the correction. We show that the a posteriori RMS of the ionosphere-free GPS phase observations for a reduced-dynamic orbit determination can be reduced from 3 to 2 mm while keeping up to 7% more data in the outlier screening compared to uncorrected observations. We also show that artifacts in the kinematic orbit and gravity field solution near the geomagnetic equator can be substantially reduced. The analytical correction is able to mitigate the equatorial artifacts. However, the analytical correction is not as successful compared to the down-weighting of problematic GPS data used in earlier studies. In contrast to the weighting approaches, up to 9–10% more kinematic positions can be retained for the heavily disturbed month March 2015 and also stronger signals for gravity field estimation in the equatorial regions are obtained, as can be seen in the reduced error degree variances of the gravity field estimation. The presented approach may also be applied to other low earth orbit missions, provided that the GPS receivers offer a sufficiently high data rate compared to the tracking loop bandwidth, and provided that the basic loop-filter parameters are known.

An Optimization Framework for the Design of Noise Shaping Loop Filters with Improved Stability Properties

A framework using semidefinite programming is proposed to enable the design of sigma delta modulator loop filters at the transfer function level. Both continuous-time and discrete-time, low-pass and band-pass designs are supported. For performance, we use the recently popularized Generalized Kalman–Yakubovic–Popov (GKYP) lemma to place constraints on the $$\mathcal {H}_\infty $$ norm of the noise transfer function (NTF) in the frequency band of interest. We expand the approach to incorporate common stability criteria in the form of $$\mathcal {H}_2$$ and $$\ell _1$$ norm NTF constraints. Furthering the discussion of stability, we introduce techniques from control systems to improve the robustness of the feedback system over a range of quantizer gains. The performance-stability trade-off is examined using this framework and motivated by simulation results.

Memristor-Based Loop Filter Design for Phase Locked Loop

The main challenge in designing a loop filter for a phase locked loop (PLL) is the physical dimensions of the passive elements used in the circuit that occupy large silicon area. In this paper, the basic features of a charge-controlled memristor are studied and the design procedures for various components of a PLL are examined. Following this, we propose a memristor-based filter design which has its resistance being replaced by a memristor in order to reduce the die area and achieve a low power consumption. We obtained a tuning range of 741–994 MHz, a stable output frequency of 1 GHz from the transfer characteristics of voltage-controlled oscillator (VCO), and an improved settling time. In addition to reduced power consumption and area occupied on the chip, our design shows a high reliability over wider range of temperature variations.

High tolerance of charge pump leakage current in Integer-N PLL frequency synthesizer for 5G networks

One of the most promising solutions for the future fifth generation communication systems is to utilize millimeter wave (mm-W) radio frequencies. There is, however, little works about Phase Locked Loop (PLL) frequency synthesizer designed for mm-W band frequency for 5G applications. This article discusses integer PLL architecture for frequency synthesis; it targets the highest range of 5G mmW [81–86] GHz using ultra-wide channel spacing of 1 GHz. This work investigates the design of a third passive loop filter for frequency synthesizer using a Phase Frequency Detector and a current switch Charge Pump such as analog devices ADF4155. The critical performance for the Charge Pump depends on the leakage current produced by the technology of its transistors. This undesirable current can have a high impact on the loop stability. However, by optimizing PLL filter parameters, the synthesizer was able to tolerate up to 117 nA. With such a high leakage current, a high performance of the system was achieved. As a result, less than −71 dBc reference spur level at 50 MHz offset frequency was ensured and 3.23 µs settling time for a hopping frequency of 5 GHz was achieved.

Phase stabilization design for radio-frequency system of the IMP HIRFL-SSC

Abstract The Radio Frequency (RF) system at the Heavy Ion Research Facility in Lanzhou of the Institute of Modern Physics was upgraded to a digital low-level radio frequency system. The key part is the phase and amplitude negative feedback system based on Digital Signal Processing (DSP) and a Field Programmable Gate Array (FPGA). This paper mainly introduces the design of the phase stabilization loop, including the principle designs for phase stabilization, loop filter design, parameter calculation, and hardware. In order to improve the performance and stability of the system, the loop filter was designed by means of zero-pole cancellation. In this paper, the derivation of the “zero pole cancellation method” is introduced in detail. The implementation structure of the loop filter in the FPGA is an ingenious design that can be applied to RF systems with different cavity loaded quality factor ( Q L ) values. For different RF systems, the parameters of proportional integral (PI) algorithm are fixed, and only one parameter Q L needs to be set. An economical compensation method for the temperature drift in the pick-up cables was designed to improve the control accuracy of the system. The phase control system was tested in long-term stability experiments, and the results show that the system has excellent phase stability over the long term, as well as parasitic phase modulation suppression.

Loop-Filter Design and Analysis for Delta-Sigma Modulators and Oversampled IIR Filters

Delta-sigma modulators spectrally shape quantization noise in discrete systems and are used extensively in communications and signal-processing systems. They are implemented using a loop-filter that processes the input and feed-back signals such that the closed loop behavior has a separate signal transfer function (STF) and noise transfer function (NTF). Loop-filter design often relies on special cases for the NTF or simplified loop-filter structures. This paper presents a method for generalized loop-filter synthesis that can implement a chosen NTF and STF independent of internal loop-filter structure or filter order. The transfer functions are formulated as polynomials of integration, $(z-1)^{-n}$ , instead of delay, $z^{-n}$ , to enable practical numerical loop-filter synthesis even for high-order and highly oversampled loop-filters. An example design shows how to use this synthesis method to design a high-order modulator that directly filters and re-modulates a direct stream digital audio signal.

A Systematic Design Method for Direct Delta-Sigma Receivers

Next generation receivers, such as the direct ΔΣ receiver (DDSR), shift the boundary between analog and digital closer to the antenna by merging the functionalities of different sub-blocks. In the DDSR, the analog components are used to their maximum potential as each stage participates in amplification, blocker filtering, anti-aliasing, and quantization noise shaping simultaneously, resulting in a compact design. To overcome the increased design complexity, the implemented DDSRs rely on common practices in receiver and ΔΣ modulator design. In this paper, we will show that the common design practices for neither receivers nor ΔΣ modulators yield optimal performance for the DDSR, and propose a systematic design method for gmC based DDSRs. The method enables improved performance and a straight-forward design flow by combining the gain partitioning, noise considerations, and loop-filter design. The developed method is demonstrated by designing a gmC based DDSR using a 28nm FDSOI CMOS process. Simulations of the DDSR indicate state-of-the-art performance.

Design, Simulation and Validation of HMC833 Loop Filter Based on Matlab

In the light of the complexity of the conventional research and design of HMC833 wideband PLL, this paper studies a design method of HMC833 loop filter based on Simulink modeling in Matlab. The dynamic parameters of loop response, such as maximum overshoot, regulation time and steady-state error, are analyzed to verify the feasibility of HMC833 loop filter design.

A Continuous-Time Delta-Sigma Modulator Using ELD-Compensation-Embedded SAB and DWA-Inherent Time-Domain Quantizer

This paper presents an energy-efficient third-order 3 bit continuous-time delta-sigma modulator (CTDSM). In this work, several architectural and circuit techniques are adopted to facilitate a low-power modulator. In the loop filter design, a single-amplifier biquad (SAB) topology is incorporated to realize the desired transfer function. With the SAB architecture, only two amplifiers are needed for implementing a third-order CTDSM. Furthermore, in the proposed SAB, the excess-loop-delay (ELD) compensation is implemented without using an extra summing circuit. For the 3 bit quantizer, a time-domain quantizer is proposed, where the data-weighted-averaging function is embedded in this quantizer to mitigate the nonlinearity issue due to the mismatch of digital-to-analog converter (DAC) unit cells. Fabricated in a 90 nm CMOS technology and clocked at 300 MHz sampling frequency, the proposed SAB-based modulator achieves a 67.2 dB SNDR and a 69.3 dB SNR in an 8.5 MHz signal bandwidth. The overall CTDSM dissipates 4.3 mW and achieves a figure-of-merit of 135 fJ/conversion-step.

Stability Criteria for GNSS Receiver Tracking Loops

This paper analyzes the stability criteria for closed loop tracking in a GNSS receiver using Bode analysis techniques. This defines the stable limits of predetection integration time (T) for a given loop filter design, including its order and noise bandwidth (Bn) in combination with all of the other components involved in the closed receiver tracking loop. The loop filter design used in this paper is based on a traditional analog design converted to digital using the bilinear transform. The shortcomings of this traditional design are briefly described, but the traditional design suffices for small T and ample phase margin. Clearly, a pilot channel in modern GNSS signals permits much longer T than allowed by the original GPS data channels, but the stability assurance must be considered in either case. The methodology applies to both data (Costas) and data-less (pilot) tracking loops. Additional insight is provided using the results of this analysis. Copyright © 2014 Institute of Navigation.

A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function

A 9.2 GHz digital phase-locked loop (PLL) that realizes a peaking-free jitter transfer function is presented. In other words, the closed-loop transfer function of the proposed digital PLL does not possess a closed-loop zero and the PLL achieves fast settling without exhibiting overshoots. While most previously reported peaking-free PLLs require additional circuit components which may adversely affect clock jitter or increase hardware complexity, the presented PLL requires only a new type of digital loop filter. The analysis on the loop dynamics and design of the optimal loop filter are presented. As for the implementation, a low-power linear time-to-digital converter (TDC) is realized with a set of three binary phase-frequency detectors whose triggering clocks are dithered using a delta-sigma modulator and phase interpolators. A digitally controlled oscillator (DCO) is implemented as a transformer-tuned LC oscillator whose frequency is set by a ratio between two digitally controlled currents. The digital PLL prototype, fabricated in a 65 nm CMOS, demonstrates 1.2 ps rms integrated jitter at 9.2 GHz and 1.58 μs settling time with 700 kHz bandwidth while dissipating 63.9 mW at a 1.2 V nominal supply.

Transmitter and receiver design at L-band and X-band for FM-CW radar altimeter

In recent years, there has been a growing interest in FM-CW (frequency modulated continuous wave) technology for military and civilian applications. FM-CW radar altimeters find applications to detect ground proximity during automatic landing in low-visibility condition, collision avoidance systems in vehicles, and ground penetrating radars for buried object detections such as landmines, pipelines, etc. The development of a low-power L-band and X-band FM-CW radar hardware and design of a third order loop filter for the phase locked loop (PLL) is the main focus of this paper. Results of laboratory trial for the calibration of FMCW radar hardware are presented to demonstrate the feasibility of operation at X band

A 1–20-GHz All-Digital InP HBT Optical Wavelength Synthesis IC

An integrated circuit (IC) for heterodyne optical phase locking in a 1-20-GHz offset range is hereby reported. The IC, implemented in a 500-nm InP HBT process, contains an emitter coupled logic digital single-sideband mixer to provide phase locking at a ± 20-GHz offset frequency, and a wideband phase-frequency detector designed to provide loop acquisition up to ±40-GHz initial frequency offset. The all-digital IC design has phase-frequency detection gain independent of IC process parameters or optical signal levels, and provides a wide offset locking range. A 100-ps delay decreases the overall loop delay, making wideband loop filter design possible. In addition, a medium-scale high-frequency logic design methodology is presented and fully discussed.

Design and analysis of a bang—bang PLL for 6.25 Gbps SerDes

An analysis illustrates the loop nonlinear performance in a bang—bang PLL. A third-order equivalent model is deduced to give an approximate evaluation of the loop parameters. The architecture of the proposed phase detector is composed of four master-slave DFFs and two XORs based on the current mode logic circuit. A no-load architecture is introduced in the XOR design. The oscillator is designed with an LC VCO implementation for the jitter requirement. A simple voltage-to-current converter is proposed to drive the loop filter. The loop filter design is described in detail, which is important to ensure the nonlinear loop stability. The chip is fabricated in a 0.18 μm CMOS technology. The experimental results show that it can achieve the frequency range of 2.995 to 3.35 GHz, and a phase noise of −118.38 dBc/Hz at 1 MHz offset. The frequency to voltage gain is 270 MHz/V. The chip consumes less than 81 mW with 1.8 V supply voltage, and it occupies a 0.5 mm2 area.

Application of Memristor-Based Controller for Loop Filter Design in Charge-Pump Phase-Locked Loops

In this work, a monotonic increasing piecewise-linear (PWL) memristor-based proportional-integral (PI) controller is analyzed. A periodic rectangular pulse current source is used as the input signal, and the proportionality constant of the PWL memristor-based PI controller is varied according to the amount of charge that passes through the memristor. A circuit is proposed to achieve zero net-charge injection for the memristor so that the memristance of the PWL memristor can be varied in the subsequent period. The proposed PWL memristor-based PI controller can be used in the design of the loop filter for the charge-pump phase-locked loop for achieving a faster dynamical response from an unlocked state to a locked state compared to conventional fixed proportional constant PI controllers.