Abstract
This paper presents an energy-efficient third-order 3 bit continuous-time delta-sigma modulator (CTDSM). In this work, several architectural and circuit techniques are adopted to facilitate a low-power modulator. In the loop filter design, a single-amplifier biquad (SAB) topology is incorporated to realize the desired transfer function. With the SAB architecture, only two amplifiers are needed for implementing a third-order CTDSM. Furthermore, in the proposed SAB, the excess-loop-delay (ELD) compensation is implemented without using an extra summing circuit. For the 3 bit quantizer, a time-domain quantizer is proposed, where the data-weighted-averaging function is embedded in this quantizer to mitigate the nonlinearity issue due to the mismatch of digital-to-analog converter (DAC) unit cells. Fabricated in a 90 nm CMOS technology and clocked at 300 MHz sampling frequency, the proposed SAB-based modulator achieves a 67.2 dB SNDR and a 69.3 dB SNR in an 8.5 MHz signal bandwidth. The overall CTDSM dissipates 4.3 mW and achieves a figure-of-merit of 135 fJ/conversion-step.
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