Design and analysis of a bang—bang PLL for 6.25 Gbps SerDes

Abstract

An analysis illustrates the loop nonlinear performance in a bang—bang PLL. A third-order equivalent model is deduced to give an approximate evaluation of the loop parameters. The architecture of the proposed phase detector is composed of four master-slave DFFs and two XORs based on the current mode logic circuit. A no-load architecture is introduced in the XOR design. The oscillator is designed with an LC VCO implementation for the jitter requirement. A simple voltage-to-current converter is proposed to drive the loop filter. The loop filter design is described in detail, which is important to ensure the nonlinear loop stability. The chip is fabricated in a 0.18 μm CMOS technology. The experimental results show that it can achieve the frequency range of 2.995 to 3.35 GHz, and a phase noise of −118.38 dBc/Hz at 1 MHz offset. The frequency to voltage gain is 270 MHz/V. The chip consumes less than 81 mW with 1.8 V supply voltage, and it occupies a 0.5 mm2 area.