Loop Filter Design Research Articles

Time-Domain Analysis of Intermodulation Distortion of Closed-Loop Class-D Amplifiers

This paper presents a time-domain analysis of the intermodulation distortion (IMD) of a closed-loop Class-D amplifier (amp) with either first- or second-order loop filter. The derived expression for the IMD indicates that there exist significant third-order intermodulation products (3rd-IMPs) within the output spectrum, which may lead to even greater distortion than the intrinsic harmonic components. In addition, the output expressions are compact, precise, and suitable for hand calculation so that the parametric relationships between the IMD and the magnitude and frequency of the input signals, as well as the effect of the loop filter design are straightforwardly investigated. In order to accurately represent the IMD performance of class-D amp, a modified testing setup is introduced to account for the dominantly large 3rd-IMPs when the International Telecommunication Union Radiocommunication Sector (ITU-R) standard is applied.

Modelling and behavioural simulation of a high-speed phase-locked loop for frequency synthesis

This study proposes the modelling and behavioural simulation of a high-speed phased-locked loop for frequency synthesis. The authors consider the second-order active lag-lead as well as the standard feedback approach of loop filter design for the system model. The s-domain transfer functions of the model for both the cases under considerations are derived for its linear analysis, considering its elemental values. Transient behaviour and stability of the model is analysed using behavioural simulations in MATLAB (Version: 7.1) which shows excellent results. Here, the authors discuss in detail the procedure for mathematical derivation of the theoretical model, taking into account both active lag-lead and standard feedback approach for the loop in the PLL model, the various aspects of methodology for simulations and their results.

An LMI-Based Method for Reference Spur Reduction in Charge-Pump Phase-Locked Loops Containing Loop Delay

This paper presents a loop-filter design method for third-order charge-pump phase-locked loops containing the loop delay. This method is derived from a z-domain phase-locked loop model. For a given loop bandwidth, we employ ripple swing control and adjust the filter pole to improve the spur performance. Another dynamic specification, the jitter peaking, is formulated as a H ∞ performance. The loop-filter design is transformed into an H ∞ optimization problem with the ripple swing constraint, which is solved using convex programming skills (linear matrix inequality, LMI). Compared to the conventional method, the method proposed in this study offers greater spur reduction without altering the loop bandwidth.

A fully integrated frequency synthesizer for a dual-mode GPS and Compass receiver

This paper presents a fully integrated frequency synthesizer for a dual-mode GPS and Compass receiver fabricated in a 0.13 μm CMOS technology. The frequency synthesizer is implemented with an on-chip symmetric inductor and an on-chip loop filter. A capacitance multiplying approach is proposed in the on-chip loop filter design for area-saving consideration. Pulse-swallow topology with a multistage noise shaping ΔΣ modulator is adopted in the frequency divider design. The synthesizer generates local oscillating signals at 1571.328 MHz and 1568.259 MHz with a 16.368 MHz reference clock by working in integer and fractional modes. Measurement results show that the phase noise of the synthesizer achieves −91.3 dBc/Hz and −117 dBc/Hz out of band at 100 kHz and 1 MHz frequency offset, separately. The proposed frequency synthesizer consumes 8.6 mA from a 1.2 V power supply and occupies an area of 0.92 mm2.

Modification of the loop filter design for a plucked string instrument

A modified loop filter design method for plucked string instruments is introduced. Previous loop filter designs do not properly represent the frequency-dependent damping of a silk stringed instrument. To solve this problem, the modified method evaluates how many harmonics are required and which portion of the sound should be chosen to effectively replicate the instrument. Then, the most reasonable filter parameters are determined based on the frequency signal-to-noise ratio of the synthesized sound.

개선된 발현악기의 루프 필터 설계 방법

본 논문에서는 발현악기 물리적 모델링에서의 개선된 루프필터 설계 방법을 제안한다. V<TEX>$\"{a}$</TEX>lim<TEX>$\"{a}$</TEX>ki가 제안한 기존의 루프필터 설계 방법은 악기의 음이 오래 지속되는 경우에는 타당하지만, 그렇지 못한 경우에는 악기 음의 주파수 의존 감쇠를 표현하지 못하는 문제점이 있다. 이를 해결하기 위해 녹음된 악기의 단위음에 대해 감쇠구간을 선택, 배음의 개수를 최소 5개부터 20개까지 변경하며 루프필터의 파라미터를 추정하고 이를 이용한 합성음과 원 신호 간 주파수 영역에서의 신호 대 잡음비가 가장 좋은 파라미터를 선택한다. 제안한 방법의 성능 검증을 위해 몸통의 구조와 현의 재질이 각각 다른 기타, 가야금, 거문고를 대상악기로 선정하였다. 제안한 방법은 배음의 지속시간에 상관없이 악기 음의 주파수 의존 감쇠를 잘 표현하는 루프필터 파라미터를 추정해 낼 수 있었다. This paper describes a development of a loop filter design in a physical modeling of the plucked string instrument. The conventional method proposed by V<TEX>$\"{a}$</TEX>lim<TEX>$\"{a}$</TEX>ki cannot estimate right parameters if a sound has either very short sustain or no sustain. In order to overcome this drawback, we propose the use of the decay region and 5 to 20 harmonics of the sound in the estimation of loop filter parameters. The most appropriate filter coefficient is chosen by frequency signal to noise ratio. To verify the performance of the proposed method, the guitar, gayageum and geomungo were selected as the target because they have different shape, structure, and material of strings. Regardless of the duration of harmonics, the proposed method was able to estimate the loop filter parameters representing frequency-dependent damping of harmonics.

Design and analysis of a CMOS passive Σ∆ ADC for low power RF transceivers

Design and analysis of a ΣΔ modulator with a passive switched capacitor loop filter is presented. Design steps for optimum loop filter design for quantization noise suppression and thermal noise reduction is outlined. Design specifications for sampling clock phase noise, reference buffer and input buffer settling is analyzed. Presented design has a 2nd-order loop filter and uses only metal-metal capacitors and thin oxide digital transistors with no additional components occupying less than 0.1 mm2 silicon area in 0.13 µm CMOS digital process. Measurement results show that the ADC achieves 80 dB peak SNR at a 100 kHz integration bandwidth with 1 pJ/sample conversion efficiency. With decimation filter power consumption of 0.22 mW at 104 MHz sampling rate, the ADC consumes only about 1 mA at 1.5 V for each channel.

General method for phase-locked loop filter analysis and design

The analysis and design of high-order phase-locked loops (PLLs) is difficult. A novel approach is presented which allows high-order loops to be viewed as a natural extension of lower-order ones. Type I low-order PLLs are considered a starting point for the design of higher type, higher-order PLLs. Starting with lower-order PLLs not only permits a comprehensive classification of all practical kinds of PLLs but also facilitates their design from a more intuitive perspective. The model presented, based on the loop filter composed of several nested first-order feedback loops, has been implemented and tested in Simulink®, confirming the ideas presented.

Loop Filter Design for Phase-Locked Loops with Guaranteed Lock-in Range

Abstract Lock-in range is one of the key parameters which govern the dynamic performance of a phase-locked loop (PLL). For low-order PLLs, coarse formulas can be derived under certain assumptions and approximation for designing loop filters to achieve the performance requirement. However, it is difficult, if not impossible, to establish such relations for high-order PLLs. In this paper, we propose a new loop filter design which, in addition to satisfying the prescribed lock-in range specification, achieves several other performance requirements as well, such as small noise bandwidth and good transient response (small settling time, small overshoot). The proposed method is applicable to PLLs of any order.

Development of a nano-displacement measurement system

This paper presents the design and development of a nano-displacement measurement system based on the SPPE framework. The system consists of an optical probe modified from a laser pickup head, as well as a holographic grating as a position reference. In order to deliver high bandwidth and better resolution measurement, H ∞ loop filter design is incorporated into the phase lock loop (PLL). Furthermore, a phase to displacement algorithm is used to recover displacement from phase output of PLL. Experiment is set up for off-line measurement and shows a measurement result with sub-nanometer resolution and satisfactory measurement repeatability.

Fourth-order PLL loop filter design technique with invariant natural frequency and phase margin

A new approach to the design of fourth-order PLL loop filters is described. The technique allows the specification of a desired attenuation at a given offset frequency whilst maintaining the same loop natural frequency and phase margin as for a third-order loop filter. The benefit of this approach is that improved attenuation is obtained at wide frequency offsets, without compromising the in-band performance of the loop, in contrast to other approaches. Design equations are presented for this technique, its performance is confirmed by loop-gain trajectory plots and the maximum possible attenuation as a function of the design parameters is established.

Mixed H∞/H2 design of digital phase‐locked loops with polytopic‐type uncertainties

AbstractA robust H∞ control method is applied to the design of loop filters for digital phase locked loop carrier phase tracking. The proposed method successfully copes with large S‐curve slope uncertainty and with a significant decision delay in the closed‐loop that may stem from the decoder and/or the equalizer there. The design problem is transformed into a state‐feedback control problem where phase and gain‐margins should be guaranteed in spite of the uncertainty. Of all the loop filters that achieve the required margins the one that minimizes an upper‐bound on the effect of the phase and the measurement noise signals is derived. Copyright © 2002 John Wiley &amp; Sons, Ltd.

Flexible loop filter design for spacecraft phase-locked receivers

A flexible loop filter design for spacecraft phase-locked receivers is proposed. The loop filter is implemented as digital hardware with coefficients that are set by registers. Either a perfect or an imperfect integrating loop filter can be effected. This flexibility is important since not one type of loop filter is preferred for all circumstances. An imperfect integrator is preferred when, as is often the case for spacecraft receivers, it is important to minimize the best-lock frequency drift of an idling loop. A perfect integrator is preferred when the tracking performance of the loop is the most important consideration.

Near-optimal PLL design for decision-feedback carrier and timing recovery

A new design method is presented for the design of PLL loop filters for carrier recovery, bit timing, or other synchronization loops given the phase noise spectrum and noise level. Unlike the conventional designs, our design incorporates a possible large decision delay and S-curve slope uncertainty. Large decision delays frequently exist in modern receivers due to, for example, a convolutional decoder or an equalizer. The new design also applies to coherent optical communications where delay in the loop limits the laser linewidth. We provide an easy-to-use complete design procedure for second-order loops. We also introduce a design procedure for higher order loops for near-optimal performance. We show that using the traditional second-order loop is suboptimal when there is a delay in the loop, and also shows large improvements, either in the amount of allowed delay, or the phase error variance in the presence of delay.

Design of loop filter in phase-locked loops

An exact method for designing loop filters in third-order PLLs is presented. The method is simple and results in a PLL with superior loop dynamics and improved output jitter while maintaining the same loop bandwidth compared to that of a PLL designed using the conventional approach. The method is readily applicable to higher order PLLs.

Hybrid Kalman/minimax filtering in phase-locked loops

A method of combining Kahnan filtering and minimax filtering is proposed and demonstrated in an application to phase-locked loop design. Kalman filtering suffers from a lack of robustness to departures from the assumed noise statistics. Minimax filtering, however, has the drawback of ignoring the engineer's (admittedly incomplete) knowledge of the noise statistics. It is shown in this paper that hybrid Kalman/minimax filtering can provide the “best of both worlds” . Phase-locked loop filter design is used in this paper to demonstrate an application of hybrid estimation.

Fuzzy logic for digital phase-locked loop filter design

The problem of robust phase-locked loop design has attracted attention for many years, particularly since the advent of the global positioning system. This paper proposes and demonstrates the use of a fuzzy PLL to estimate the time-varying phase of a sinusoidal signal. It is shown via simulation results that fuzzy PLL's offer performance comparable to analytically derived PLL's (e.g. Kalman filters and H/sub /spl infin estimators) when the phase exhibits high dynamics and high noise. The fuzzy PLL rules are optimized using a gradient descent method and a genetic algorithm.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Third-Order Loop Filter Design for Acceleration-Rate Tracking

A perfect third-order loop filter design that can be implemented as a digital filter is obtained which minimizes the noiseless steady-state acceleration rate (jerk) error for a fixed loop noise bandwidth. Simulations were performed to obtain transient responses of the third-order loop plus a sample fourth-order loop under a jerk input. The results enable one to obtain a loop design that minimizes the loop noise bandwidth required for a given steady-state jerk error and thus obtain better noise jitter performance.