Logic Primitives Research Articles

Expanding the Set of Three-Input Logic Functions in Inverted T-Shaped TFETs

Three-input logic primitives show high efficiency in logic synthesis compared to traditional two-input logic, which encourages researchers to implement three-input logic gates with emerging nanotechnologies. This paper demonstrates a compact implementation of three-input monotone logic gates based on the inverted T-shaped TFET. Firstly, based on the gate coupling mechanism in the novel inverted T channel, the BTBT current can be suppressed in the vertical or horizontal region to achieve the channel strobe. Therefore, the typical three-input monotone logic functions, Majority, OrAnd, and AndOr, are successfully implemented on a single transistor. Then, a simplified potential model describing gate coupling is established to describe the impact of key device parameters on the logic behavior. Combined with TCAD simulation, the design rules of devices with different logic functions are given. Finally, a series of three-input monotonic logic gates are designed and verified. The results show that the use of the proposed TFETs can effectively save the number of transistors in the three-input logic gate, which indicates that the three-input TFET is a compact and flexible candidate for three-input logic gates.

Digital circuits and neural networks based on acid-base chemistry implemented by robotic fluid handling

Acid-base reactions are ubiquitous, easy to prepare, and execute without sophisticated equipment. Acids and bases are also inherently complementary and naturally map to a universal representation of “0” and “1.” Here, we propose how to leverage acids, bases, and their reactions to encode binary information and perform information processing based upon the majority and negation operations. These operations form a functionally complete set that we use to implement more complex computations such as digital circuits and neural networks. We present the building blocks needed to build complete digital circuits using acids and bases for dual-rail encoding data values as complementary pairs, including a set of primitive logic functions that are widely applicable to molecular computation. We demonstrate how to implement neural network classifiers and some classes of digital circuits with acid-base reactions orchestrated by a robotic fluid handling device. We validate the neural network experimentally on a number of images with different formats, resulting in a perfect match to the in-silico classifier. Additionally, the simulation of our acid-base classifier matches the results of the in-silico classifier with approximately 99% similarity.

More Than a Device: Function Implementation in a Multi-Gate Junctionless FET Structure

The miniaturization of the transistor sizes to keep up with Moore's Law in Integrated Circuits (ICs) is rapidly approaching the physical limits. To push the horizons of Moore's Law, among the various approaches available in the literature, single device-based computing shows promise by achieving more functionality in a smaller footprint. However, a single device-based computing approach either mainly embeds only the primitive logic hence inefficient in performance, or requires exotic devices like spin logic devices, and memristor which involve non-conventional costly manufacturing steps. Previously, we introduced the concept of embedding logic in a single device based on Crosstalk Computing, where deterministic signal interference between nano-metal lines is leveraged for logic computation. This paper elaborates upon the methodology of realizing complex Boolean functions through TCAD-based modeling and simulations, quantifying results, and compares against existing approaches. Core to our approach is a multi-gate Junctionless FET-based device, methodical placement of the independent gates, manipulation of device parameters, and dimension. This paper shows the implementation of various complex logic functions along with the primitive gates in the proposed device. Our benchmark results show 8x density benefits and 8x less power consumption on average than CMOS-based implementation. For the case of delay, elementary and complex logic devices show comparable characteristics with 14 nm PTM counterparts. Such realization of complex functions in a stand-alone device is compatible with the existing fabrication process.

The reemergence of the language-of-thought hypothesis: Consequences for the development of the logic of thought.

Quilty-Dunn et al. defended the reemergence of language-of-thought hypothesis (LoTH). My commentary builds up implications for the study of the development of our logical capacities. Empirical support for logically augmented LoT systems calls for the investigation of their logical primitives and developmental origin. Furthermore, Quilty-Dunn et al.'s characterization of LoT helps the quest for the foundation of logic by dissociating logical cognition from natural language.

Cost-efficient method for inverter reduction and proper placement in quantum-dot cellular automata

ABSTRACT The Quantum-dot Cellular Automata (QCA), an emerging technology, is observed to be the most viable solution to current CMOS. It is capable of finding solutions to challenges, like high power consumptionand device density. The elementary logic primitives are the majority gate, inverter and wire. In QCA, two different event cell orientations for the realisation of the inverter are available, where the diagonally oriented structure (DOS) is mostly utilised in logic synthesis. However, considering the cell misalignment and displacement, the DOS prevails with a more stable polarised output. But the use of DOS increases cell count which increases the area of the circuit. So, it is desirable to minimise the inverter in a circuit due to the non-availability of the simple logic unit of the inverter. In this paper, two algorithms are proposed for the synthesis of cost-efficient QCA circuits from any boolean function to minimize logic primitives. The proposed role-based mechanism for boolean function synthesis results in the reduction of inverter gate, circuit size, QCA cost and power dissipation. The efficiency of the proposed algorithms has been verified with the realization of standard functions, adders and symmetric functions. A significant improvement in inverter reduction has been reported.

Adapting the RACER Architecture to Integrate Improved In-ReRAM Logic Primitives

Modern computing applications based upon machine learning can incur significant data movement overheads in state-of-the-art computers. Resistive-memory-based <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">processing-using-memory</i> (PUM) can mitigate this data movement by instead performing computation <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in situ</i> (i.e., directly within memory cells), but device-level limitations restrict the practicality and/or performance of many PUM architecture proposals. The RACER architecture overcomes these limitations, by proposing efficient peripheral circuitry and the concept of bit-pipelining to enable high-performance, high-efficiency computation using small memory tiles. In this work, we extend RACER to adapt easily to different PUM logic families, by (1) modifying the device access circuitry to support a wide range of logic families, (2) evaluating three logic families proposed by prior work, and (3) proposing and evaluating a new logic family called OSCAR that significantly relaxes the switching voltage constraints required to perform logic with resistive memory devices. We show that the modified RACER architecture, using the OSCAR logic family, can enable practical PUM on real ReRAM devices while improving performance and energy savings by 30% and 37%, respectively, over the original RACER work.

Circuit-Level Exploration of Ternary Logic Using Memristors and MOSFETs

In recent decades, the performance of binary computers has escalated through transistor scaling. However, due to the impotent forecasts of transistor scaling, ternary systems are regaining attention. Among many ternary device candidates, a passive device called memristor that is based on resistance switching is considered a good candidate when integrated with MOSFETs. Therefore, in this paper, we design various terna-ry logic based on memristors and MOSFETs from primitive logic to sequential logic and perform a thorough diagnosis for circuit design. We highlight design issues that should be resolved (e.g., signal distortion and high static current) and present practical solutions such as “Strength Design.” Then, we report a proper design methodology of sequential circuits considering the spike phenomena of memristor-based gates. We present 16 novel ternary logic cells and circuitry, including the design of the first balanced ternary full-adder (TFA) and memristor-based ternary pulsed-latch (MTPL). By our TFA, we emphasize that it is possible to design the most practical ternary circuits using memristors and MOSFETs. Our TFA uses 97 transistors and 87 memristors, which is the most reasonable TFA design that has the highest potential to be implemented in the near future. Besides, the proposed MTPL uses 16 transistors and 10 memristors, and it occupies only 72.7% of the silicon area, compared to the master-slave ternary flip-flop.

Novel VLSI Architectures and Micro-Cell Libraries for Subscalar Computations

Parallelism is the key to enhancing the throughput of computing structures. However, it is well established that the presence of data-flow dependencies adversely impacts the exploitation of such parallelism. This paper presents a case for a new computing paradigm namely subscalar digital arithmetic which is aimed at mitigating this issue. It proposes to break up atomic data and atomic operations thereon into sub-atomic data fragments and sub-atomic partial operations. Such a break-up exposes hitherto unexploited levels of parallelism by way of allowing overlap of operations even if data-dependent. Surprisingly this enhanced exploitation of latent parallelism comes with a favorable impact on the area-power characteristics of corresponding computing structures which is contrary to common sense. The paper also proposes a novel micro cell library with logic primitives at corresponding subscalar levels. The synthesized circuits for several sequential benchmarks show an order of magnitude improvement in their area-throughput figure-of-merit (FOM).

Non-blocking programmable delay line with minimal dead time and tens of picoseconds jitter

We report a non-blocking high-resolution digital delay line based on an asynchronous circuit design. Field-programmable gate array logic primitives were used as a source of delay and optimally arranged using combinatorial optimization. This approach allows for an efficient trade-off of the resolution and a delay range together with a minimized dead time operation. We demonstrate the method by implementing the delay line adjustable from 23ns up to 1635ns with a resolution of 10ps. We present a detailed experimental characterization of the device focusing on thermal instability, timing jitter, and pulse spreading, which represent three main issues of the asynchronous design. We found a linear dependence of the delay on the temperature with the slope of 0.2 ps K-1 per logic primitive. We measured the timing jitter of the delay to be in the range of 7-165ps, linearly increasing over the dynamic range of the delay. We reduced the effect of pulse spreading by introducing pulse shrinking circuits and reached the overall dead time of 4-22.5ns within the dynamic range of the delay. The presented non-blocking delay line finds usage in applications where the dead time minimization is crucial, and tens of picoseconds of excess jitter is acceptable, such as in many advanced photonic networks.

Fault-tolerant control of an error-corrected qubit.

Quantum error correction protects fragile quantum information by encoding it into a larger quantum system1,2. These extra degrees of freedom enable the detection and correction of errors, but also increase the control complexity of the encoded logical qubit. Fault-tolerant circuits contain the spread of errors while controlling the logical qubit, and are essential for realizing error suppression in practice3-6. Although fault-tolerant design works in principle, it has not previously been demonstrated in an error-corrected physical system with native noise characteristics. Here we experimentally demonstrate fault-tolerant circuits for thepreparation, measurement, rotation and stabilizer measurement of a Bacon-Shor logical qubit using 13 trapped ion qubits. When we compare these fault-tolerant protocols to non-fault-tolerant protocols, we see significant reductions in the error rates of the logical primitives in the presence of noise. The result of fault-tolerant design is an average state preparation and measurement error of 0.6 per cent and a Clifford gate error of 0.3 per cent after offline error correction. In addition, we prepare magic states with fidelities that exceed the distillation threshold7, demonstrating all of the key single-qubit ingredients required for universal fault-tolerant control. These results demonstrate that fault-tolerant circuits enable highly accurate logical primitives in current quantum systems. With improved two-qubit gates and the use of intermediate measurements, a stabilized logical qubit can be achieved.

In-sensor classification with boosted race trees

When extremely low-energy processing is required, the choice of data representation makes a tremendous difference. Each representation (e.g., frequency domain, residue coded, and log-scale) embodies a different set of tradeoffs based on the algebraic operations that are either easy or hard to perform in that domain. We demonstrate the potential of a novel form of encoding, race logic, in which information is represented as the delay in the arrival of a signal. Under this encoding, the ways in which signal delays interact and interfere with one another define the operation of the system. Observations of the relative delays (for example, the outcome of races between signals) define the output of the computation. Interestingly, completely standard hardware logic elements can be repurposed to this end and the resulting embedded systems have the potential to be extremely energy efficient. To realize this potential in a practical design, we demonstrate two different approaches to the creation of programmable tree-based ensemble classifiers in an extended set of race logic primitives; we explore the trade-offs inherent to their operation across sensor, hardware architecture, and algorithm; and we compare the resulting designs against traditional state-of-the-art hardware techniques.

Robust Circuit and System Design for General-Purpose Computational Resistive Memories

Resistive switching devices (memristors) constitute a promising device technology that has emerged for the development of future energy-efficient general-purpose computational memories. Research has been done both at device and circuit level for the realization of primitive logic operations with memristors. Likewise, important efforts are placed on the development of logic synthesis algorithms for resistive RAM (ReRAM)-based computing. However, system-level design of computational memories has not been given significant consideration, and developing arithmetic logic unit (ALU) functionality entirely using ReRAM-based word-wise arithmetic operations remains a challenging task. In this context, we present our results in circuit- and system-level design, towards implementing a ReRAM-based general-purpose computational memory with ALU functionality. We built upon the 1T1R crossbar topology and adopted a logic design style in which all computations are equivalent to modified memory read operations for higher reliability, performed either in a word-wise or bit-wise manner, owing to an enhanced peripheral circuitry. Moreover, we present the concept of a segmented ReRAM architecture with functional and topological features that benefit flexibility of data movement and improve latency of multi-level (sequential) in-memory computations. Robust system functionality is validated via LTspice circuit simulations for an n-bit word-wise binary adder, showing promising performance features compared to other state-of-the-art implementations.

Design and Analysis of Secure Emerging Crypto-Hardware Using HyperFET Devices

The emergence of new devices to be used in low-power applications are expected to reach impressive performance compared to those obtained by equivalent CMOS counterparts. However, when used in lightweight security applications, these emerging paradigms are required to be reliable and safe enough during the task of protecting important and valuable data. In this work, the usage of HyperFET devices for security applications has been analyzed and new paradigms for enhancing security against Power Analysis attacks have been developed for the first time. To perform this analysis, classical dual-precharge logic primitives implemented with 14nm FinFET have been upgraded to incorporate HyperFET devices. The proposed primitives incorporating HyperFETs, as well as a 4-bit Substitution box of PRIDE algorithm as demonstrative example, have been designed and simulated using predictive models. Simulation-based Differential Power Analysis attacks demonstrate high improvements in security levels in a x25 factor at least, with negligible degradation in performance. This first approach could be easily extensible to other ciphers or crypto-circuits, where the incorporation of HyperFET devices will enhance security for most future applications.

Physical Limitations on Fundamental Efficiency of SET-Based Brownian Circuits

Brownian circuits are based on a novel computing approach that exploits quantum fluctuations to increase the efficiency of information processing in nanoelectronic paradigms. This emerging architecture is based on Brownian cellular automata, where signals propagate randomly, driven by local transition rules, and can be made to be computationally universal. The design aims to efficiently and reliably perform primitive logic operations in the presence of noise and fluctuations; therefore, a Single Electron Transistor (SET) device is proposed to be the most appropriate technology-base to realize these circuits, as it supports the representation of signals that are token-based and subject to fluctuations due to the underlying tunneling mechanism of electric charge. In this paper, we study the physical limitations on the energy efficiency of the Single-Electron Transistor (SET)-based Brownian circuit elements proposed by Peper et al. using SIMON 2.0 simulations. We also present a novel two-bit sort circuit designed using Brownian circuit primitives, and illustrate how circuit parameters and temperature affect the fundamental energy-efficiency limitations of SET-based realizations. The fundamental lower bounds are obtained using a physical-information-theoretic approach under idealized conditions and are compared against SIMON 2.0 simulations. Our results illustrate the advantages of Brownian circuits and the physical limitations imposed on their SET-realizations.

A bottom-up approach to creating an ontology for medication indications.

The study sought to learn if it were possible to develop an ontology that would allow the Food and Drug Administration approved indications to be expressed in a manner computable and comparable to what is expressed in an electronic health record. A random sample of 1177 of the 3000+ extant, distinct medical products (identified by unique new drug application numbers) was selected for investigation. Close manual examination of the indication portion of the labels for these drugs led to the development of a formal model of indications. The model represents each narrative indication as a disjunct of conjuncts of assertions about an individual. A desirable attribute is that each assertion about an individual should be testable without reference to other contextual information about the situation. The logical primitives are chosen from 2 categories (context and conditions) and are linked to an enumeration of uses, such as prevention. We found that more than 99% of approved label indications for treatment or prevention could be so represented. While some indications are straightforward to represent, difficulties stem from the need to represent temporal or sequential references. In addition, there is a mismatch of terminologies between what is present in an electronic health record and in the label narrative. A workable model for formalizing drug indications is possible. Remaining challenges include designing workflow to model narrative label indications for all approved drug products and incorporation of standard vocabularies.

High-Density Memristor-CMOS Ternary Logic Family

This paper presents the first experimental demonstration of a ternary memristor-CMOS logic family. We systematically design, simulate and experimentally verify the primitive logic functions: the ternary AND, OR and NOT gates. These are then used to build combinational ternary NAND, NOR, XOR and XNOR gates, as well as data handling ternary MAX and MIN gates. Our simulations are performed using a 50-nm process which are verified with in-house fabricated indium-tin-oxide memristors, optimized for fast switching, high transconductance, and low current leakage. We obtain close to an order of magnitude improvement in data density over conventional CMOS logic, and a reduction of switching speed by a factor of 13 over prior state-of-the-art ternary memristor results. We anticipate extensions of this work can realize practical implementation where high data density is of critical importance.

Semisupervised Learning via Axiomatic Fuzzy Set Theory and SVM.

In this article, we present a semantic semisupervised learning (Semantic SSL) approach targeted at unifying two machine-learning paradigms in a mutually beneficial way, where the classical support vector machine (SVM) learns to reveal primitive logic facts from data, while axiomatic fuzzy set (AFS) theory is utilized to exploit semantic knowledge and correct the wrongly perceived facts for improving the machine-learning model. This novel semisupervised method can easily produce interpretable semantic descriptions to outline different categories by forming a fuzzy set with semantic explanations realized on the basis of the AFS theory. Besides, it is known that disagreement-based semisupervised learning (SSL) can be viewed as an excellent schema so that a co-training approach with SVM and the AFS theory can be utilized to improve the resulting learning performance. Furthermore, an evaluation index is used to prune descriptions to deliver promising performance. Compared with other semisupervised approaches, the proposed approach can build a structure to reflect data-distributed information with unlabeled data and labeled data, so that the hidden information embedded in both labeled and unlabeled data can be sufficiently utilized and can potentially be applied to achieve good descriptions of each category. Experimental results demonstrate that this approach can offer a concise, comprehensible, and precise SSL frame, which strikes a balance between the interpretability and the accuracy.

Generative Grammar: A Meaning First Approach.

The theory of language must predict the possible thought—signal (or meaning—sound or sign) pairings of a language. We argue for a Meaning First architecture of language where a thought structure is generated first. The thought structure is then realized using language to communicate the thought, to memorize it, or perhaps with another purpose. Our view contrasts with the T-model architecture of mainstream generative grammar, according to which distinct phrase-structural representations—Phonetic Form (PF) for articulation, Logical Form (LF) for interpretation—are generated within the grammar. At the same time, our view differs from early transformational grammar and generative semantics: We view the relationship between the thought structure and the corresponding signal as one of compression. We specify a formal sketch of compression as a choice between multiple possible pronounciations balancing the desire to transmit information against the effort of pronounciation. The Meaning First architecture allows a greater degree of independence between thought structures and the linguistic signal. We present three arguments favoring this type of independence. First we argue that scopal properties can be better explained if we only compare thought structures independent of the their realization as a sentence. Secondly, we argue that Meaning First architecture allows contentful late insertion, an idea that has been argued for in Distributed Morphology already, but as we argue is also motivated by the division of the logical and socio-emotive meaning content of language. Finally, we show that only the Meaning First architecture provides a satisfying account of the mixing of multiple languages by multilingual speakers, especially for cases of simultaneous articulation across two modalities in bimodal speakers. Our view of the structure of grammar leads to a reassessment of priorities in linguistic analyses: while current mainstream work is often focused on establishing one-to-one relationships between concepts and morphemes, our view makes it plausible that primitive concepts are frequently marked indirectly or unpronounced entirely. Our view therefore assigns great value to the understanding of logical primitives and of compression.

In‐Memory Database Query

In recent years, several in‐memory logic primitives were proposed where bit‐wise logical operations are performed in memory by exploiting the physical attributes of memristive devices organized in a crossbar array. However, a convincing real‐world application for in‐memory logic and its experimental validation are still lacking. Herein, the application of database query where a database is stored in an array of binary memristive devices is presented. The queries are formulated in terms of bulk bit‐wise operations and are executed in memory by exploiting Kirchhoff's current summation law. The concept is experimentally demonstrated by executing error‐free queries on a small 4 × 8 selector‐less phase‐change memory crossbar. The impact of crossbar size, resistance of routing wires, and interdevice variability on the accuracy of the logical operations are studied through numerical and circuit‐level simulations. Finally, a system for cascaded query is proposed that combines the in‐memory logic with conventional digital logic and its functionality is verified on a healthcare‐related database. It is estimated that an 11‐step long query is executed in 36 ns, consuming 560 μW, thus achieving an energy efficiency of 166 TOPS/W.

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

As we approach the end of Moore’s law, many alternative devices are being explored to satisfy the performance requirements of modern integrated circuits. At the same time, the movement of data between processing and memory units in contemporary computing systems (‘von Neumann bottleneck’ or ‘memory wall’) necessitates a paradigm shift in the way data is processed. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic which has been found to be an efficient logic primitive due to its expressive power. In this review, the efficiency of majority logic is analyzed from the perspective of in-memory computing. Recently reported methods to implement majority gate in Resistive RAM array are reviewed and compared. Conventional CMOS implementation accommodated heterogeneity of logic gates (NAND, NOR, XOR) while in-memory implementation usually accommodates homogeneity of gates (only IMPLY or only NAND or only MAJORITY). In view of this, memristive logic families which can implement MAJORITY gate and NOT (to make it functionally complete) are to be favored for in-memory computing. One-bit full adders implemented in memory array using different logic primitives are compared and the efficiency of majority-based implementation is underscored. To investigate if the efficiency of majority-based implementation extends to n-bit adders, eight-bit adders implemented in memory array using different logic primitives are compared. Parallel-prefix adders implemented in majority logic can reduce latency of in-memory adders by 50–70% when compared to IMPLY, NAND, NOR and other similar logic primitives.