Robust Circuit and System Design for General-Purpose Computational Resistive Memories

Felipe Pinto,Ioannis Vourkas

doi:10.3390/electronics10091074

Abstract

Resistive switching devices (memristors) constitute a promising device technology that has emerged for the development of future energy-efficient general-purpose computational memories. Research has been done both at device and circuit level for the realization of primitive logic operations with memristors. Likewise, important efforts are placed on the development of logic synthesis algorithms for resistive RAM (ReRAM)-based computing. However, system-level design of computational memories has not been given significant consideration, and developing arithmetic logic unit (ALU) functionality entirely using ReRAM-based word-wise arithmetic operations remains a challenging task. In this context, we present our results in circuit- and system-level design, towards implementing a ReRAM-based general-purpose computational memory with ALU functionality. We built upon the 1T1R crossbar topology and adopted a logic design style in which all computations are equivalent to modified memory read operations for higher reliability, performed either in a word-wise or bit-wise manner, owing to an enhanced peripheral circuitry. Moreover, we present the concept of a segmented ReRAM architecture with functional and topological features that benefit flexibility of data movement and improve latency of multi-level (sequential) in-memory computations. Robust system functionality is validated via LTspice circuit simulations for an n-bit word-wise binary adder, showing promising performance features compared to other state-of-the-art implementations.

Highlights

Even though, in CMOS-based computing systems, the von Neumann architecture has been dominant for several decades, given the current pressure of exponentially rising amounts of data, the modern computing systems are calling for major architectural changes [1]
While important efforts are being placed towards the development of synthesis algorithms for in-memory computing architectures [9,10], the revolutionary step will be the development of an arithmetic logic unit (ALU) entirely based on in-memory logic operations with memristors
We validate functionality, showing the voltage applied to the bitline, the evolution of the logic state of three vertically aligned memristors, and the output of the corresponding SA connected to OL1

Summary

Introduction

In CMOS-based computing systems, the von Neumann architecture has been dominant for several decades, given the current pressure of exponentially rising amounts of data, the modern computing systems are calling for major architectural changes [1]. It consists of group-accessed transistors as cross-point selector devices 4 of 25 which otherwise severely affect the performance of pass. If the inherent variability of HRS and LRS of memristors affects the resulting VIN1,2 input voltages to a similar degree, this could potentially lead to erroneous logic computations at the CMOS XOR gate. In this context, an enhanced scouting logic scheme was proposed in Reference [26], but it used a more complex 1T1R array to achieve higher reliability of logic operations.

Performance Comparison in Presence of HRS and LRS Variability

Overall Design Description

Simulation Results for Individual Memory and Logic Operations

Simulation Results for n-Bit Binary Addition

Performance Comparison Results

Conclusions