Abstract
This paper presents the first experimental demonstration of a ternary memristor-CMOS logic family. We systematically design, simulate and experimentally verify the primitive logic functions: the ternary AND, OR and NOT gates. These are then used to build combinational ternary NAND, NOR, XOR and XNOR gates, as well as data handling ternary MAX and MIN gates. Our simulations are performed using a 50-nm process which are verified with in-house fabricated indium-tin-oxide memristors, optimized for fast switching, high transconductance, and low current leakage. We obtain close to an order of magnitude improvement in data density over conventional CMOS logic, and a reduction of switching speed by a factor of 13 over prior state-of-the-art ternary memristor results. We anticipate extensions of this work can realize practical implementation where high data density is of critical importance.
Highlights
C ONVENTIONAL digital systems compute using binary logic, where only two possible values are available in the Boolean space
(b) Fig. 1. (a) Schematic of a typical back end of the line (BEOL) integration of a resistive randomaccess memory (RRAM) switching layer with a standard CMOS process (b) Transmission electron microscopy (TEM) image of the high-speed switching metal-insulator-metal memristor built for logic implementation
Our gates achieve stateof-the-art performance compared to other memristor-CMOS designs in terms of area, power and speed
Summary
C ONVENTIONAL digital systems compute using binary logic, where only two possible values are available in the Boolean space. Commercial solid-state drives use quad level cells (QLC) for high storage density [1], [2], but come at the cost of slow write times. (a) Schematic of a typical BEOL integration of a resistive randomaccess memory (RRAM) switching layer with a standard CMOS process (b) Transmission electron microscopy (TEM) image of the high-speed switching metal-insulator-metal memristor built for logic implementation. Our gates achieve stateof-the-art performance compared to other memristor-CMOS designs in terms of area, power and speed. We achieve data density improvements over conventional CMOS gates by a factor of 3.9–25.5 times, and speed improvements by a factor of 13 over state-of-the-art high-speed memristor ternary logic implementations. A study of area, power and switching speed are provided to compare against other memristor-CMOS ternary logic circuits
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