More Than a Device: Function Implementation in a Multi-Gate Junctionless FET Structure

Abstract

The miniaturization of the transistor sizes to keep up with Moore's Law in Integrated Circuits (ICs) is rapidly approaching the physical limits. To push the horizons of Moore's Law, among the various approaches available in the literature, single device-based computing shows promise by achieving more functionality in a smaller footprint. However, a single device-based computing approach either mainly embeds only the primitive logic hence inefficient in performance, or requires exotic devices like spin logic devices, and memristor which involve non-conventional costly manufacturing steps. Previously, we introduced the concept of embedding logic in a single device based on Crosstalk Computing, where deterministic signal interference between nano-metal lines is leveraged for logic computation. This paper elaborates upon the methodology of realizing complex Boolean functions through TCAD-based modeling and simulations, quantifying results, and compares against existing approaches. Core to our approach is a multi-gate Junctionless FET-based device, methodical placement of the independent gates, manipulation of device parameters, and dimension. This paper shows the implementation of various complex logic functions along with the primitive gates in the proposed device. Our benchmark results show 8x density benefits and 8x less power consumption on average than CMOS-based implementation. For the case of delay, elementary and complex logic devices show comparable characteristics with 14 nm PTM counterparts. Such realization of complex functions in a stand-alone device is compatible with the existing fabrication process.