Logic Swing Research Articles

Low power self-controllable voltage level and low swing logic based 11T SRAM cell for high speed CMOS circuits

This article explains about the design of a new low power 11T SRAM cell. In this proposed method, two voltage sources are used, one is connected to the bit line and the other is connected to the bit bar line respectively in order to eliminate the swing voltage at the output nodes of the bit and bit bar lines. When the SRAM cell is in working mode the dynamic power dissipation is reduced by minimizing the swing voltage. Self-controllable voltage level is a technique in which PMOS transistor acts as a switch and NMOS transistors act as a resistors coupled in series reduces leakage current when the transistors change its state from sleep to active and vice versa. Reduce in leakage current causes the diminution in static power dissipation. To avoid the data retention difficulty, maximum voltage is supplied to the circuit during the active mode and reduced voltage is supplied during the stand-by mode. By using Synopsys EDA tool, all simulation results of power dissipation, delay, transistor utilization, power delay product and energy-delay product of the proposed 11T SRAM cell and other existing models of SRAM cell has been carried out in 30 nm CMOS technology.

Silicon nanowire CMOS NOR logic gates featuring one-volt operation on bendable substrates

In this study, we propose complementary metal-oxide−semiconductor (CMOS) NOR logic gates consisting of silicon nanowire (NW) arrays on bendable substrates. A circuit consisting of two p-channel NW field-effect transistors (NWFETs) in series and two n-channel NWFETs in parallel is constructed to operate a two-input CMOS NOR logic gate. The NOR logic gates operate at a low supply voltage of 1 V with a rail-to-rail logic swing and a high voltage gain of approximately −3.0. The exact NOR logic functionality is achieved owing to the superior electrical characteristics of the well-aligned p- and n-NWFETs, which are obtained using conventional Si-based CMOS technology. Moreover, the NOR logic gates exhibit stable characteristics and have good mechanical properties. The proposed bendable NW CMOS NOR logic gates are promising building blocks for future bendable integrated electronics.

Silicon nanowire ratioed inverters on bendable substrates

In this study, we demonstrate the performance of silicon nanowire (SiNW)n-metal oxide semiconductor (MOS) and p-MOS ratioed inverters that are fabricated on bendable substrates. The electrical characteristics of the fabricateddevices can be controlled by adjusting the load voltage. The logic swings of then- and p-MOS ratioed inverters at a low supply voltage of 1 V are 80% and 96%, respectively. The output voltage level of the p-MOS ratioed inverter is close to rail-to-rail operation. The device also exhibits stable characteristics with goodfatigue properties. Our bendable SiNW ratioed inverters show promise asa candidate building block for future bendable electronics.

Tunnel Transistor-Based Reliable and Energy Efficient Computing Architectures with Circuit and Architectural Co-Design at Low VDD

Tunnel field-effect transistors (TFETs) as low voltage device options have attracted recent attention for energy efficient circuit designs with CMOS technology scaling. This paper presents the circuit and architectural co-design approach for designing reliable and energy efficient architectures (adder cells) for new computing platforms at supply voltages. At circuit level TFET-based 28-transistor static logic design (28T) and 24-transistor transmission gate logic design (24T) have been explored. At architectural level, multiplexer (MUX)-based 22-transistor full adder design (22T) is proposed. Performance of TFET-based architectures have also been benchmarked with 20[Formula: see text]nm double gate Si FinFET technology. It has been seen that with FinFET technology 24T design is not effective in terms of energy efficiency and reliability (due to the large leakage currents in transmission gate logic topology). 28T design is the best in reliability perspective (in terms of reduced over shoots, full logic swing and reduced glitch duration etc.) and 22T design to be energy efficient option. It has been demonstrated in this paper that TFET’s steep slope characteristics enable the 24T design to have similar reliability characteristics like 28T design and energy efficiency like 22T design. TFET-based 22T design has [Formula: see text]91% smaller energy delay product (EDP) and [Formula: see text]84.4% less power delay product (PDP) in comparison to the low threshold voltage (LVT) FinFET 22T design at 0.2[Formula: see text]V VDD.

Nano-scale Transistors with Circuit Interaction for Designing Energy-Efficient and Reliable Adder Cells at Low VDD

ABSTRACTDesigning reliable and energy-efficient circuits with CMOS technology scaling is a pressing challenge at scaled supply voltages. This paper provides design insights and circuit interaction approach with two such emerging devices, double-gate FinFETs and tunnel field effect transistors (TFETs), for designing basic computing building blocks such as adder cells. At the circuit level, TFET-based transmission gate logic 1-bit full adder (TGLA) and improved transmission gate logic 1-bit full adder (ITGLA) cells have been proposed and designed taking into unidirectional conduction and ambipolar currents of TFETs into consideration. The performance of TFET designs has been benchmarked with 20 nm double-gate Si FinFET technology. ITGLA design is a better energy-efficient option in comparison to TGLA design with FinFETs but has reduced reliability. It has been demonstrated that the steep slope characteristics of TFETs enable both TGLA and ITGLA designs to display improved energy efficiency and reliability characteristics (in the form of reduced overshoot, reduced glitches, improved logic swing, etc.). These characteristics make TFETs desirable candidates for reliable and energy-efficient computing architectures at scaled supply voltages.

A New Device-Physics-Based Noise Margin/Logic Swing Model of Surrounding-Gate MOSFET Working on Subthreshold Logic Gate

In this paper, we present a device-physics-based noise margin (NM)/logic swing (LS) model of surrounding-gate (SRG) MOSFET working on subthreshold CMOS logic gates. Based on the device physics and equivalent transistor model, theoretical analysis of the main dc parameters, including LS and NM for SRG MOSFET operating in low-voltage condition, is revealed. It is shown that the device parameters, such as the thick silicon thickness $t_{\mathrm{ si}}$ , thick gate oxide thickness $t_{\mathrm{ ox}}$ , and short channel length $L_{g}$ , can severely degrade the LS and NM. On the contrary, both the small subthreshold slope $\eta $ and balanced transistor strength S induced by device parameters can suppress the NM and LS degradation efficiently. The required minimum supply voltage $V_{\mathrm{ dd,min}}$ for the subthreshold CMOS logic gate is derived by the criterion of the NM ≥ KT/ $q$ to ensure the correct logic gate operation. Being similar to DIBL, both NM and LS degraded by the device parameters can also be uniquely determined and controlled by the scaling factor according to scaling theory. Finally, considerations on the impact of process/voltage/temperature variation are also included for NM/LS behavior analysis.

Design of Low Power and Area Efficient Full Adder using Modified Gate Diffusion Input

The low power techniques are becoming more important due to rapid development of portable digital applications; demand for high-speed and low power consumption.GDI (Gate Diffusion Input) is one of the low power and area efficient technique. GDI requires less number of transistors compared to CMOS technology. The basic cell of GDI consists of two transistors where three terminals i.e Gate, Source and Drain considered as inputs. Therefore, it is helpful for low power, delay and area. But the disadvantage of GDI is its output has poor logic swing .This paper presents low power high performance multiplexer based full adder design in CADENCE VIRTUOSO GPDK 45nm Technology. The power consumption comparison is also made based on CMOS and GDI design technique.

High-Performance WSe2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits.

Because of their extraordinary structural and electrical properties, two-dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (∼38) and small static power (picowatts), paving the way for low power electronic system in 2D materials.

High performance of full swing logic inverter using all n-types amorphous ZnSnO and SiZnSnO thin film transistors

A high performance inverter consisting of amorphous zinc-tin-oxide (a-ZTO) thin film transistor (TFT) with enhancement mode and amorphous silicon-zinc-tin-oxide (a-SZTO) TFT with depletion mode has been fabricated by using only n-type metal-oxide thin film transistors. The turn on voltages of ZTO and SZTO TFTs showed positive value of 1.17 V and negative value of −5 V, respectively. High voltage gain of about 25 has been obtained by using implemented inverter with good switching characteristics even with all n-type thin film transistors.

Vertical NOR-logic circuits constructed using nanoparticle films on plastic substrates

In this study, a NOR-logic circuit is constructed by the vertical stacking of three individual thin-film transistors (TFTs) with the channels of solution-processed chalcogenide nanoparticle (NP) films on a plastic substrate. The NOR-logic circuit consists of two p-type HgTe NP-based TFTs, which act as drivers, and one n-type HgSe NP-based TFT, which plays the role of an active load. The logic operation is observed with a substantial difference in Vout between the logic state of “00” and the other logic states, and the logic swing is ∼60%.

Si-Nanowire-Array-Based NOT-Logic Circuits Constructed on Plastic Substrates Using Top–Down Methods

Si-nanowire (NW)-array-based NOT-logic circuits were constructed on plastic substrates. The Si-NW arrays were fabricated on a Si wafer through top-down methods, including conventional photolithography and crystallographic wet etching, and transferred onto the plastic substrates. Two field-effect transistors were fabricated on a single Si-NW array composed of five nanowires aligned in parallel and connected in series to form NOT-logic circuits. The excellent flexibility of the fabricated device was confirmed by bending-cycling tests. The voltage-transfer curve of the NOT-logic circuits showed an inverting operation with a logic swing of -92% and voltage gain of -2.5.

Nanocrystal-Based Complementary Inverters Constructed on Flexible Plastic Substrates

We demonstrate a nanocrystal (NC)-based complementary inverter constructed on a flexible plastic substrate. The NC-based complementary inverter consists of n-type HgSe NC- and p-type HgTe NC-based thin-film transistors (TFTs). Solid films on a plastic substrate obtained from HgSe and HgTe nanocrystals by thermal transformation are utilized as the n- and p-channel layers in these TFTs, respectively. The electrical properties of these component TFTs on unstrained and strained substrates are characterized and the performance of the inverter on the flexible substrate is investigated. The inverter on the unstrained substrate exhibits a logic gain of about 8, a logic swing of 90%, and a noise margin of 2.0 V. The characteristics of the inverter are changed under tensile and compressive strains, but not very significantly. Moreover, a comparison of the electrical characteristics of the n- and p-channel TFTs and the inverter is made in this paper.

A Reliable, Process-Sensitive-Tolerant Hybrid Sense Amplifier for Ultralow Power SRAM

A novel ultra high speed, compact and least sensitive to process variation, hybrid sense amplifier is designed for ultra low power SRAM. Precisely sized current mode circuit (CMC) is designed to provide differential current from bit-lines. We eliminate the global sensing stage to save silicon area and sized the output buffers to achieve full logic swing at the output of proposed sense amplifier. The proposed design improves the sensing delay and shows excellent tolerance to process variations as compared to best published latch type sense amplifier. Extensive post layout simulation results based on 45nm standard CMOS technology have verified that 38.8% reduction in sensing delay and 83.6% reduction in power dissipation is achieved compared to the best published designs under similar cell current (Icell) and bitline capacitances. The total power delay product is 0.22fJ. Furthermore, the new design can operate down to a supply voltage of 0.6V. These attribute of the proposed sense amplifier makes it judiciously appropriate for the use in the contemporary wireless sensor SRAM macro, which continuously pine for ultra low power and high-speed characteristics. In addition, the proposed design exhibits low sensitivity to bitline and dataline capacitance, capacitance mismatch. 

550 $^{\circ}\hbox{C}$ Integrated Logic Circuits using 6H-SiC JFETs

This letter reports the design, fabrication, and electrical characteristics of inverter, NAND, and NOR logic circuits using 6H-silicon carbide (SiC) depletion-mode junction field-effect transistors. All circuits function with high performance at temperatures from 25 °C to 550 °C. The core inverter has an outstanding dc characteristic transfer function with a steep slope, including a gain of >; -20 up to 500 °C, and a logic threshold that is well centered in the logic swing. NOR and NAND gates were likewise tested in this temperature range, and dynamic characteristics are presented. This SiC technology provides a platform for applications demanding reliable digital circuits at temperatures higher than 300 °C, well beyond the capability of silicon technology.

Full swing logic inverter with amorphous SiInZnO and GaInZnO thin film transistors

A high-performance n-channel metal-oxide-semiconductor inverter implemented consisting of enhancement mode driving thin-film transistor with amorphous Ga-In-Zn-O (a-GIZO) and depletion mode load with amorphous Si-In-Zn-O (a-SIZO) is demonstrated. The threshold voltage of the post-annealed a-SIZO load thin film transistor (TFT) exhibits negative value while the threshold voltage of the GIZO driving TFT exhibits positive value. The proposed inverter composed of a-SIZO and a-GIZO TFT shows much improved switching characteristics with higher voltage gain.

Complementary Circuit with Self-Alignment Organic/Oxide Thin-Film Transistors

Complementary logic circuits with self-alignment organic/oxide thin-film transistors (TFTs) were investigated. The layout and process steps of a self-alignment bottom-contact-type organic TFT and a top-contact type oxide TFT with a common layout pattern of the gate, source, and drain electrodes were proposed, and an integrated circuit was realized. The estimated field-effect mobilities, threshold voltages, and on-off ratios of the organic and oxide TFTs were 0.16 and 2.2 cm2 V-1 s-1, 2.2 and 2 V, and 3×103 and 5.2×106, respectively. From the complementary inverter characteristics, the voltage gain was 13 and the logic swing was 9.8 V at an applied voltage of 10 V. From the switching characteristics of the inverter, the rise and fall times were 18 and 46 µs, respectively. The operations of the NAND and NOR logic circuit configurations were confirmed, and the maximum operational frequency of NAND logic was estimated to be over 100 kHz.

Monolithically integrated enhancement/depletion-mode AlGaN/GaN HEMT D flip-flop using fluorine plasma treatment

Depletion-mode and enhancement-mode AlGaN/GaN HEMTs using fluorine plasma treatment were integrated on one wafer. Direct-coupled FET logic circuits, such as an E/D HEMT inverter, NAND gate and D flip-flop, were fabricated on an AlGaN/GaN heterostructure. The D flip-flop and NAND gate are demonstrated in a GaN system for the first time. The dual-gate AlGaN/GaN E-HEMT substitutes two single-gate E-HEMTs for simplifying the NAND gate and shrinking the area, integrating with a conventional AlGaN/GaN D-HEMT and demonstrating a NAND gate. E/D-mode D flip-flop was fabricated by integrating the inverters and the NAND gate on the AlGaN/GaN heterostructure. At a supply voltage of 2 V, the E/D inverter shows an output logic swing of 1.7 V, a logic-low noise margin of 0.49 V and a logic-high noise margin of 0.83 V. The NAND gate and D flip-flop showed correct logic function demonstrating promising potential for GaN-based digital ICs.

Inductorless 8.9 mW 25 Gb/s 1:4 DEMUX and 4 mW 13 Gb/s 4:1 MUX in 90 nm CMOS

A low-power inductorless 1:4 DEMUX and a 4:1 MUX for a 90 nm CMOS are presented. The DEMUX can be operated at a speed of 25 Gb/s with the power supply voltage of 1.05 V, and the power consumption is 8.9 ㎽. The area of the DEMUX core is 29 × 40 ㎛². The operation speed of the 4:1 MUX is 13 Gb/s at a power supply voltage of 1.2 V, and the power consumption is 4 ㎽. The area of the MUX core is 30 × 18 ㎛². The MUX/DEMUX mainly consists of differential pseudo-NMOS. In these MUX/DEMUX circuits, logic swing is nearly rail-torail, and a low Vdd. The component circuit is more scalable than a CML circuit, which is commonly used in a high-performance MUX/DEMUX. These MUX/DEMUX circuits are compatible with conventional CMOS logic circuit, and it can be directly connected to CMOS logic gates without logic level conversion. Furthermore, the circuits are useful for core-to-core interconnection in the system LSI or chip-to-chip communication within a multi-chip module, because of its low power, small footprint, and reasonable operation speed.

Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis

In this paper, the DC behavior of subthreshold CMOS logic is analyzed in a closed form for the first time in the literature. To this aim, simplified large-signal and small-signal models of MOS transistors in subthreshold region are first developed. After replacing transistors with these equivalent models, analysis of the main DC parameters of CMOS logic gates is presented. In particular, the change in the DC characteristics shape due to operation at ultra-low voltages is analyzed in detail, evaluating analytically the degradation in the logic swing, the symmetry and the steepness of the transition region, as well as the change in the unity-gain points position. The resulting expressions permit to gain an insight into the basic dependence of DC behavior on design and device parameters. The noise margin is explicitly evaluated and modeled with a very simple expression. Interestingly, analysis shows that the noise margin deviates from the ideal half-swing value by an amount that linearly depends on the logarithm of the pn -ratio. Analysis permits to evaluate the minimum supply voltage that ensures correct operation of CMOS logic (i.e., positive noise margin). Previously proposed rule of thumbs to evaluate minimum voltage are also theoretically justified. Moreover, the impact of pMOS/nMOS unbalancing on DC characteristics is analyzed from a design perspective. Considerations on the impact of process/voltage/temperature variations are also introduced. Results are validated through extensive simulations in a 65-nm CMOS technology.

Single ZnO nanowire inverter logic circuits on flexible plastic substrates

In this study, inverter logic circuits on a plastic substrate are built with two top-gate FETs in series on a single ZnO nanowire. The voltage transfer characteristics of the ZnO nanowire-based inverter logic circuit exhibit a clear inverting operation. The logic swing, gain and transition width of the inverter logic circuit is about 90 %, 1.03 and 1.2 V, respectively. The result of mechanical bending cycles of the inverter logic circuit on a plastic substrate shows that the stable performance is maintained even after many hundreds of bending cycles.