Design of Low Power and Area Efficient Full Adder using Modified Gate Diffusion Input

Abstract

The low power techniques are becoming more important due to rapid development of portable digital applications; demand for high-speed and low power consumption.GDI (Gate Diffusion Input) is one of the low power and area efficient technique. GDI requires less number of transistors compared to CMOS technology. The basic cell of GDI consists of two transistors where three terminals i.e Gate, Source and Drain considered as inputs. Therefore, it is helpful for low power, delay and area. But the disadvantage of GDI is its output has poor logic swing .This paper presents low power high performance multiplexer based full adder design in CADENCE VIRTUOSO GPDK 45nm Technology. The power consumption comparison is also made based on CMOS and GDI design technique.