A New Device-Physics-Based Noise Margin/Logic Swing Model of Surrounding-Gate MOSFET Working on Subthreshold Logic Gate

Abstract

In this paper, we present a device-physics-based noise margin (NM)/logic swing (LS) model of surrounding-gate (SRG) MOSFET working on subthreshold CMOS logic gates. Based on the device physics and equivalent transistor model, theoretical analysis of the main dc parameters, including LS and NM for SRG MOSFET operating in low-voltage condition, is revealed. It is shown that the device parameters, such as the thick silicon thickness $t_{\mathrm{ si}}$ , thick gate oxide thickness $t_{\mathrm{ ox}}$ , and short channel length $L_{g}$ , can severely degrade the LS and NM. On the contrary, both the small subthreshold slope $\eta $ and balanced transistor strength S induced by device parameters can suppress the NM and LS degradation efficiently. The required minimum supply voltage $V_{\mathrm{ dd,min}}$ for the subthreshold CMOS logic gate is derived by the criterion of the NM ≥ KT/ $q$ to ensure the correct logic gate operation. Being similar to DIBL, both NM and LS degraded by the device parameters can also be uniquely determined and controlled by the scaling factor according to scaling theory. Finally, considerations on the impact of process/voltage/temperature variation are also included for NM/LS behavior analysis.