Elliptical nanowire FET: Modeling the short-channel subthreshold current caused by interface-trapped-charge and its evaluation for subthreshold logic gate

Abstract

Based on the quasi-3D potential approach, quasi-3D scaling theory, drift-diffusion model, and equivalent flat-band voltage shift, a short-channel subthreshold current caused by the interface-trapped-charge is modeled for the elliptical nanowire FET. With the subthreshold current, the logic swing (LS) of the subthreshold logic gate composed of elliptical nanowire FET is theoretically evaluated. It indicates that the positive interface-trapped-charge can degrade the high output voltage (V OH ) due to its increased/decreased the subthreshold current of N-FET/P-FET. However, the negative interface-trapped-charge can decrease/increase the subthreshold current of N-FET/P-FET, which hence deteriorates the low output voltage (V OL ). Both degradation of the subthreshold current and LS (i.e., ΔI sub and ΔLS) caused by short-channel effects (SCEs) can be well-controlled by the properly selected scaling factor of α. With the minimum scaling factor, the minimum LS degradation for the subthreshold logic gate can be uniquely determined. • Providing the robust interface-trapped-charged-degraded subthreshold model for the elliptical MOSFET. • Examining how the short-channel-effects together with the interface-trapped-charge-effects affect the logic swing of the subthreshold logic gate.