Nano-scale Transistors with Circuit Interaction for Designing Energy-Efficient and Reliable Adder Cells at Low VDD

Abstract

ABSTRACTDesigning reliable and energy-efficient circuits with CMOS technology scaling is a pressing challenge at scaled supply voltages. This paper provides design insights and circuit interaction approach with two such emerging devices, double-gate FinFETs and tunnel field effect transistors (TFETs), for designing basic computing building blocks such as adder cells. At the circuit level, TFET-based transmission gate logic 1-bit full adder (TGLA) and improved transmission gate logic 1-bit full adder (ITGLA) cells have been proposed and designed taking into unidirectional conduction and ambipolar currents of TFETs into consideration. The performance of TFET designs has been benchmarked with 20 nm double-gate Si FinFET technology. ITGLA design is a better energy-efficient option in comparison to TGLA design with FinFETs but has reduced reliability. It has been demonstrated that the steep slope characteristics of TFETs enable both TGLA and ITGLA designs to display improved energy efficiency and reliability characteristics (in the form of reduced overshoot, reduced glitches, improved logic swing, etc.). These characteristics make TFETs desirable candidates for reliable and energy-efficient computing architectures at scaled supply voltages.