Performance benchmarking of tunnel transistors for energy efficient 4-bit adder architectures at low V<SUB align="right">DD

Abstract

Tunnel field-effect transistors (TFETs) have emerged as one of the most promising post-CMOS transistor technologies. This paper presents design analysis and benchmarking of TFET based three different 1-bit full adders (8T-XOR Logic, 6T-XOR Logic and MUX Based) are used for designing 4-bit adders in two different topologies targeting a VDD below 500 mV. These topologies are 22T/18T 1-bit full adder based 4-bit carry propagate adder (22T/18TCPA) and multiplexer logic 1-bit full adder based 4-bit carry propagate adder (MCPA). The performance of TFET based 4-bit adder topologies has been benchmarked with 20 nm double gate Si FinFET technology. Tunnel FETs are desirable candidates for building energy efficient and reliable arithmetic blocks with supply voltage scaling. We demonstrate that TFET's steep slope characteristics enable the 22TCPA design to be energy efficient option along with improved reliability and 18TCPA design is the best in terms of energy efficiency and reliability amongst all designs at low supply voltages.