Abstract
Tunnel FETs as steep slope devices have attracted attention for achieving energy efficiency at low supply voltages. This paper presents the design of Hetero-junction Tunnel FET (HTFET) based logic gates for static and dynamic logic topologies for the first time. Comparison is also done with 20nm Si FinFET technology with supply voltage scaling. Due to the steep slope characteristics, HTFET topologies have improved energy efficiency in comparison to Si FinFET configurations. It has been observed that HTFET static logic gate (two input NAND) is ~60% more energy efficient then Si FinFET static logic gate. One of the key findings from this work is that HTFET dynamic logic gates outperform HTFET static gates and FinFET designs in terms of energy efficiency due to HTFET's steep slope, low static power and reduced delay values. The HTFET dynamic logic gate has ~65% less energy consumption than HTFET static NAND gate and ~56% less energy consumption than FinFET dynamic NAND gate at V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</inf> =0.2V.
Published Version
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