III-V/Si staggered heterojunction based source-pocket engineered vertical TFETs for low power applications

Abstract

Abstract This article presents a comparative study on the performance characteristics of some vertical tunnel field effect transistor (TFET): conventional all-Si TFET with pocket, In0.53Ga0.47As/Si heterojunction TFET with pocket and GaSb/Si heterojunction TFET with pocket. Low band gap materials like In0.53Ga0.47As and GaSb are used here in source region of the TFETs which reduces the tunnel width to cause a greater number of carriers to tunnel through the source-channel heterojunction. Proposed III-V/Si heterojunction TFETs offer better sub-threshold swing, ION/IOFF ratio and lower threshold voltage over the conventional all-Si vertical TFET with pocket at VDS = 0.5 V. Along with the DC parameters, different analog/RF parameters are also extensively studied for all three TFET devices. In addition to this, effect of temperature on device DC performance is thoroughly investigated for the presented TFETs. Linearity parameters are also studied for all the three devices to assure better performance in a communication system at high-frequency.