Device and Circuit-Level Performance Comparison of Vertically Grown All-Si and Ge/Si Hetero-Junction TFET

Abstract

This work reports device and circuit-level performance comparison between Ge/Si heterojunction vertical tunnel field effect transistor (TFET) and All-Si vertical tunnel field effect transistor (TFET). To improve the subthreshold performance, a source pocket is sandwiched between source and channel region of the presented TFETs. Germanium which has lower bandgap than silicon is considered in the source region of the proposed TFET to reduce the tunneling width which in turn inhibits more electrons to tunnel through the interface between source and channel region. Device-level performance benefits in terms of DC and RF parameters of the vertically grown Ge/Si heterojunction TFET is thoroughly investigated and compared with the All-Si vertical TFET using SILVACO ATLASTM TCAD tool. In addition, circuit-level performance comparison of the presented TFETs is made by considering some basic digital circuits like an inverter and a five-stage ring oscillator using CADENCE Virtuoso tool.