Low power self-controllable voltage level and low swing logic based 11T SRAM cell for high speed CMOS circuits

Abstract

This article explains about the design of a new low power 11T SRAM cell. In this proposed method, two voltage sources are used, one is connected to the bit line and the other is connected to the bit bar line respectively in order to eliminate the swing voltage at the output nodes of the bit and bit bar lines. When the SRAM cell is in working mode the dynamic power dissipation is reduced by minimizing the swing voltage. Self-controllable voltage level is a technique in which PMOS transistor acts as a switch and NMOS transistors act as a resistors coupled in series reduces leakage current when the transistors change its state from sleep to active and vice versa. Reduce in leakage current causes the diminution in static power dissipation. To avoid the data retention difficulty, maximum voltage is supplied to the circuit during the active mode and reduced voltage is supplied during the stand-by mode. By using Synopsys EDA tool, all simulation results of power dissipation, delay, transistor utilization, power delay product and energy-delay product of the proposed 11T SRAM cell and other existing models of SRAM cell has been carried out in 30 nm CMOS technology.