Analysis of static noise margin and power dissipation of a proposed low voltage swing 8T SRAM cell

Abstract

In this paper analysis of noise margin and power dissipation of a novel low power proposed 8T SRAM cell has been reported. In the proposed structure two voltage sources are connected with the Bit line and the other connected with the Bit bar line are used in order to reduce voltage swings at the output nodes of bit and bit bar line during the write operation. Static noise margin values have been calculated at different transistor cell ratios and different transistor pull-up ratios. Similarly the power dissipations at different supply voltages, temperatures and bit line capacitances are calculated. Results of static noise margin and power dissipations are compared to those of conventional 6T and 11T SRAM cells. The proposed SRAM cell has better stability at different cell ratios and pull-up ratios in comparison to 6T and 11T SRAM cells. Power dissipation in the proposed SRAM cell is less at different supply voltages, temperatures and bit line capacitances in comparison to 6T and 11T SRAM cells. The simulation has been done in 350nm CMOS environment by using BSim4 model. Microwind 3.1 is used for schematic design.