A novel low power 8T SRAM cell design using lower and upper self controllable voltage level techniques in 45 nm technology

Abstract

This paper proposes a novel low power 8T SRAM cell for write operation. In the proposed structure, two voltage sources VS1 and VS2 are connected with the bit line and the bit bar line, respectively. These voltage sources reduce the swing voltage and reduction in swing voltage causes the reduction in dynamic power dissipation of the proposed SRAM cell. Also, two different leakage power reduction techniques called upper self controllable voltage level (USVL) and lower self controllable voltage level (LSVL) have been proposed and applied individually and in combination with the proposed 8T SRAM for the reduction of leakage current. Both the leakage current and power dissipation results are compared with those of conventional 6T and 7T SRAM cells reported in different literatures. Static noise margin is also analysed during write operation for stability purpose. The proposed SRAM cell has lesser leakage current in comparison to conventional 6T SRAM cell and also dissipates the least amount of power and yields better stability in comparison to both 6T and 7T SRAM cells. The authors use 45 nm CMOS technology with 0.5 volt power supply for simulation purpose. Microwind 3.1 software is used for schematic design and simulation.