Linearity Figure Of Merit Research Articles

Assessment of temperature and ITCs on single gate L-shaped tunnel FET for low power high frequency application

In a vertical TFET structure, controllability over the gate is enhanced because of the favorable electrostatic potential and tunneling under the entire gate region by preventing the direct source to drain tunneling. For an L-shaped TFET, the Band-to-Band-Tunneling (BTBT) is perpendicular and parallel to the channel length. Also, it has a higher I on (ON-current) with suppressed ambipolar current (low I ambi ) and is more scalable than other vertical BTBT mechanism-based TFET structures. The reliability of n-type single gate L-shaped TFET (SG-nLTFET) is investigated by examining: (1) impact of temperature (Temp K ) variation (from 260 K to 460 K) and (2) Interface trap charge (ITCs) polarity at fixed charge density on analog /RF /linearity figure of merits (FOMs). The obtained results reveal that change in polarity of ITCs at the Si/HfO 2 interface,modifies the analogue characteristics of the SG-nLTFET significantly in terms of turn-on voltage as well as I on . The temperature sensitivity of SG-nLTFET device indicates that the ShockleyReadHall (SRH) and Trap-Assisted-Tunneling (TAT) phenomenon dominates at lower gate bias and degrades the I on /I off ratio at high temperatures. On the other hand, the BTBT mechanism predominates in the subthreshold regime of transfer characteristics. Furthermore, the results reveal that the off-state current (I off ) degrades dramatically at high temperatures. According to the empirical analysis, SG-nLTFET is insusceptible to Positive-ITCs (Donor trap charges, P-ITCs) present at Si/HfO 2 interface in comparison to Negative-ITCs (Acceptor trap charges, N-ITCs).

Impact of Self-Heating on Linearity Performance of In0.53Ga0.47As-Based Gate-All-Around MOSFETs

In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As based gate-all-around (GAA) MOSFETs are very promising for high frequency applications because they deliver higher current and transconductance compared to their Si counterparts. In ultra-short GAA nanowire (NW) and nanosheet (NS) MOSFETs, heat accumulation in the channel region has become a serious issue as it raises the average lattice temperature several degrees above the ambient temperature ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{T}_{\text A}$ </tex-math></inline-formula> ). The increment in the average lattice temperature, also known as self-heating, degrades current driving capability and the linearity behaviour of the devices. In this work, the impact of self-heating on the linearity performance of In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As based GAA NW and NS MOSFETs has been investigated with the assistance of thermally calibrated TCAD simulation results. The effects of structural parameters of NW and NS MOSFETs, like gate oxide thickness (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OX</sub> ), the diameter of nanowire (d), the width of nanosheet (W), and the number of nanowires/nanosheets (N) on linearity performance have been extensively studied using the linearity figure of merits, such as VIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , and IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> . Moreover, the impact of self-heating mitigating techniques on the linearity performance of devices has also been explored in this work.

Influence of dielectric material near tunnel junction on analog/ RF and linearity figure of merits in hetero dielectric ( HG ) TFET : A detailed study

Influence of dielectric material near tunnel junction on analog/ <scp>RF</scp> and linearity figure of merits in hetero dielectric ( <scp>HG</scp> ) <scp>TFET</scp> : A detailed study

Study on impact of ferroelectric layer thickness on RF /analog and linearity parameters in ferroelectric‐FinFET

In this paper, we systematically investigated the effect of ferroelectric (FE) layer thickness (tFE) on transfer and RF/analog characteristics such as transconductance (gm), total gate capacitance (Cgg), cut off frequency (ft), transconductance frequency product, and unilateral power gain in Ferroelectric-FinFET (Fe-FinFET) through 3D TCAD simulator. Further, we highlighted the influence of tFE on linearity figure of merits (FoMs), higher order harmonics (gm2 and gm3), voltage intercept points (VIP2 and VIP3), third order power intercept point (IIP3), third order intermodulation distortion (IMD3), and 1-dB compression point (1-dB comp. Pnt.) for Fe-FinFET. Moreover, the harmonic distortion (HD) parameters like second and third order harmonic distortion (HD2 and HD3) and total harmonic distortion (THD) are reported taking tFE as a parameter. The noise spectral densities of Fe-FinFET taking tFE as parameter is also highlighted. The scaling of tFE has a significant impact on RF/analog parameters and these RF/analog FoMs are a function of tFE. It is also perceived that linearity and HD parameters are dependent on scaling of tFE. Results reveal that with increase in tFE, RF/analog characteristics degrades, whereas, superior linearity FoMs is achieved. It is also seen that HD parameters are improved with increased in tFE value. The increased in tFE leads to increase in noise spectral densities. Finally, the comparative study of electrical parameters of this work with the existing literature is investigated.

Performance and Analysis of Stack Junctionless Tunnel Field Effect Transistor

To overcome the fabrication complexity and achieve a better switching ratio is a major grave concern for applications in semiconductor devices. In this regards, a novel stack gate-oxide junctionless double-gate tunnel field effect transistor with low work-function livestrip (LWLS-SGO-JL-TFET) has been investigated in this manuscript. This structure serves as an alternative solution to improve the performance of device. For this, device structure has comprised of two isolated gates such as polarity gate and control gate with the platinum (work-function = 5.93 eV) and hafnium (work-function = 4.3 eV) respectively, over the N+-type doped silicon substrate for the formation of Tunnel Field Effect Transistor as a like doped conventional TFETs (Tunnel Field Effect Transistors) to overcome fabrication complexity. Since ON state current plays important role in switching ratio and subthreshold swing. Therefore, a dual layer oxide (stack) has introduced in junctionless TFETs to get further improvement in ON state current due to the better capacitive coupling between gate and substrate. Under this condition, the performance improvement is still required of dual oxide juntionless TFETs. Hence, a live strip has inserted at the source side in dual oxide layer to improve the ON state current which helps in gain of device and design of analogue and RF circuits. Moreover, we have also examined the impact of low work-function of live strip on dual oxide Junctionless TFETs in terms of DC, analog/RF and linearity figures of merit (FOMs) of the device. All simulation have been carried out using the technology computer aided design (TCAD) tool. This study shows that proposed device is an appropriate for ultra low power high frequency applications.

Deep Insight into DC/RF and Linearity Parameters of a Novel Back Gated Ferroelectric TFET on SELBOX Substrate for Ultra Low Power Applications

In this manuscript, a novel back gated ferroelectric heterojunction TFET on SELBOX substrate (BG-Fe-HJ-STFET) has been proposed. Ferroelectric oxide is considered as gate dielectric material along with SiO2 in a vertical gate stacked manner in the proposed TFET with SELBOX (BG-Fe-HJ-STFET) to improve overall sub-threshold performance of the device. The proposed TFET (BG-Fe-HJ-STFET) is found to achieve a lower sub-threshold swing value of 38.6 mV/decade (below the Boltzmann limit of 60 mV/decade) compared to the SELBOX TFET without ferro dielectric structure (BG- HJ-STFET). Different RF figures of merit such as cut-off frequency, transit time and gain-bandwidth product (GBP) are thoroughly investigated and comparison study is performed for both the TFETs presented for study. Further, the linearity figure of merits (FOMs) like VIP2, VIP3, IIP3, IMD3, and 1-dB compression point has been analyzed for both the TFETs under study. Result shows that the proposed TFET with ferro dielectric gate material (BG-Fe-HJ-STFET) outperforms the SELBOX TFET without ferro dielectric gate material (BG-HJ-STFET) in all aforementioned aspects. Performance analysis is carried out using Silvaco TCAD tool for both TFETs structures.

Impact of interface trap charges on device level performances of a lateral/vertical gate stacked Ge/Si TFET-on-SELBOX-substrate

This paper reports the TCAD based investigation of the DC/RF and linearity characteristics of a newly proposed dual-material (DM) laterally-stacked (LS) SiO2/HfO2 heterojunction-TFET-on-SELBOX substrate (LS-STFET). Device-level performance comparison is made between the proposed TFET with a dual-material (DM) vertically-stacked (VS) SiO2/HfO2 heterojunction-TFET-on-SELBOX substrate (VS-STFET). Low bandgap material Ge is used in the source region to form a Ge (source)/Si (channel) heterojunction for enhancing the ON-state current of the presented TFETs. The effects of both donor (+ ve) and acceptor (−ve) type interface trap charges at the channel/SiO2 region on the DC, analogue/RF and linearity figure of merits have been analyzed for both the devices under study. The LS-STFET is shown to possess higher ON-state current and smaller subthreshold swing (SS) over the VS-STFET. In addition, the LS-STFET is shown to have better DC, analog/RF and linearity performance over VS-STFET in the presence of the donor and acceptor interface trap charges.

An Improved Analog/RF and Linearity Performances with Small-Signal Parameter Extraction of Virtually Doped Recessed Source/Drain Dopingless Junctionless Transistor for Radio-Frequency Applications

A small-signal radio-frequency (RF) parameters extraction model along with analog/RF and linearity distortion performance analysis are realized for virtually doped (VD) recessed source/drain dopingless junctionless transistor (Re S/D DLJLT) via 3-D device simulations. A simple and accurate RF non-quasi-static (NQS) model is developed to directly extract the extrinsic and intrinsic parasitic components through Y-parameters in OFF and ON-state respectively. Furthermore, direct comparison of DC, analog/RF, linearity figure of merits (FOMs), and Y-parameter extractions are made with recessed source/drain junction transistor (Re S/D JT) with identical threshold voltage (Vth) and device dimensions at GHz frequency range. Virtual doping, due to charge-plasma (CP) concept, provides N+ source/drain (S/D) regions by choosing a most convenient metal work function (WF = 3.9 eV; Hafnium) at S/D. Re S/D provides reduced series resistance without an increase in gate-drain Miller capacitance leading to improved drive current. In addition, the present device uses an intrinsic channel and does not require to be doped at S/D resulting in dopingless junctionless transistor (DLJLT). For both devices, gate length (L) is taken as 30 nm, which separated into control gate (L1) and screen gate (L2) and 3-D simulations are carried out by varying control to screen gate length ratios (CSLR) to obtain optimum results. Obtained results disclose that Re S/D DLJLT provides considerably improved performances in terms of DC, analog/RF, linearity, transient, and small-signal admittance parameters over Re S/D JT due to improved drive current and reduced short channel effects (SCEs). Accordingly, for high-performance RF applications, Re S/D DLJLT may be preferred over Re S/D JT due to significantly enhanced cut-off frequency (up to 0.399 THz) and maximum oscillation frequency (up to 1.226 THz).

Dependence of RF/Analog and Linearity Figure of Merits on Temperature in Ferroelectric FinFET: A Simulation Study.

This article presents a simulation study of the impact of variation in temperature on the transfer characteristics and the RF/analog performance like transconductance ( gm ), gate capacitance ( Cgg ), cutoff frequency ( ft ), and transconductance frequency product (TFP) of the ferroelectric FinFET (Fe-FinFET). In addition, the impact of temperature on the linearity parameters such as higher order harmonics ( gm2 and gm3 ), second- and third-order voltage intercept points (VIP2 and VIP3), third-order power-intercept point (IIP3), third-order intermodulation distortion (IMD3), and 1-dB compression point is estimated for wide variation of temperature in the Fe-FinFET. It is seen that temperature has a significant impact on the RF/analog and linearity parameters, and these figure of merits (FoMs) are the functions of temperature. Analysis reports that RF/analog parameters are suppressed, whereas the linearity FoMs are improved as temperature changed from 250 to 350 K.

Proposal of Charge Plasma Based Recessed Source/Drain Dopingless Junctionless Transistor and its Linearity Distortion Analysis for Circuit Applications

Linearity and intermodulation distortion (IMD) analysis examined major reliability issues that arise due to the non-linear behavior of the devices in analog/RF circuit applications. In this paper, by means of virtually doped (dopingless), a distinctive influence of charge-plasma (CP) is proposed on novel dual metal gate (DMG; control and screen gate) recessed source/drain (Re S/D) transistor; envisaged as recessed source/drain dopingless junctionless transistor (Re S/D DLJLT). Re S/D structure diminishes series resistance without any accretion of the gate-drain Miller capacitance resulting in a better drive current (ION). DC and analog characteristics have been further improved by adopting CP conception for induction of N+ S/D region owing to favorably well-chosen metal work function electrodes. The main intent of this paper is to appraise the linearity and IMD performance characteristics of the Re S/D DLJLT using 2-D numerical calculations and scrutinize the distinction with recessed source/drain junction transistor (Re S/D JT) with identical dimensions. Device linearity parameters comprise of transconductance (Gm1) and its higher order coefficients (Gm2 and Gm3), second and third order voltage and input intercept point (VIP2, VIP3, and IIP3) third order IMD, and 1 − dB compression point (1 − dBCP) which are based on possible structural and control to screen gate length ratios (CSLR) variations in both devices. The influences of parametric modifications on linearity Figure of merits (FOMs) explore optimum bias point by investigating optimum structural with CSLR variations. The detailed investigation of linearity FOMs of the impact on different device engineering has been carried out. The obtained outcomes divulge that proposed device delivers appreciably enhanced linearity FOMs as compared to Re S/D JT.

Optimization of a Hetero-Structure Vertical Tunnel FET for Enhanced Electrical Performance and Effects of Temperature Variation on RF/Linearity Parameters

A new hetero-structure vertical tunnel field effect transistor is proposed and investigated using Sentaurus Technology Computer-aided Design simulation. Since the direction of the gate electric field is in alignment with the direction of tunneling of electrons, a higher on state current is attained. Optimization of the geometric dimension of the proposed structure is carried out to yield its optimum performance. As temperature variation affects the device performance, temperature analysis of the proposed structure is performed in which both the off state leakage current and the average subthreshold swing increases with temperature. Further investigation on the influence of temperature variation is carried out in terms of Analog/RF parameters such as transconductance, gate capacitance, cut-off frequency, transconductance frequency product and linearity figure of merits. It is observed that the proposed structure attains superior linearity performance and lower distortion at higher gate voltage with rise in temperature and is less affected by temperature variation at lower gate voltage.

Polarization Engineering of AlGaN/GaN HEMT With Graded InGaN Sub-Channel for High-Linearity X-Band Applications

We report on the power and linearity performance of metal-organic chemical vapor deposition grown polarization-engineered novel structure that combines the AlGaN/GaN high-electron-mobility transistor with a graded InGaN sub-channel layer. The fabricated transistors with composite two-dimensional(2D) and three-dimensional(3D) electron channels showed nearly flat transconductance and power gain profiles. The maximum f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> values of 18 GHz and 38 GHz were measured for 0.7-μm gate-length transistors. Load-pull measurement at 10 GHz revealed a maximum output power of 2.2 W/mm. Two-tone measurement at 10 GHz showed an excellent OIP3 of 38 dBm for 150-μm device width and a corresponding linearity figure of merit OIP3/P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DC</sub> of 9.7 dB. These results suggest that InGaN-based composite 2D-3D channel transistors could be useful for high-frequency applications requiring high linearity.

Approach to suppress ambipolarity and improve RF and linearity performances on ED‐Tunnel FET

This work reports a dual metal bipolar gate-based electrically doped tunnel field-effect transistor (DMBG-ED-TFET) which overcomes the ambipolarity issue and gives improved radio frequency (RF) and linearity metrics. The formations of n + , p + drain and source regions in this device is performed by applying polarity biases at polarity gate (PG)-1 and PG-2 with 1.2 and −1.2 V. In DMBG-ED-TFET, the gate is alienated into three subdivisions and each subdivision named as tunnel gate (M1), BG (M2) and auxiliary gate (M3) with their respective work functions as ϕ M 1 , ϕ M 2 and ϕ M 3 , respectively. Finally, some existent applications were applied on a proposed device with different possible combinations (work function). Those different possible combinations of work function, the proposed device (DMBG-ED-TFET) gives superior results with ϕ M 1 = ϕ M 3 < ϕ M 2 , where ϕ M 1 is near to source region because to increase the I on current and ϕ M 3 is located near the drain region to overwhelm the ambipolarity. Additionally, the application of work function engineering on the proposed device results in improving the DC characteristics along with analogue/RF and linearity figure of merits (VIP3, IIP3 and IMD3) also discussed.

Effect of trench depth and gate length shrinking assessment on the analog and linearity performance of TGRC-MOSFET

This paper discusses the impact of trench depth (Negative Junction Depth (NJD)) and gate length (LG) shrinking on analog and linearity performance of Transparent Gate Recessed Channel (TGRC) MOSFET with an aim to achieve a reliable and high performance transistor. It is found that device enhances the ION by 38% and thereby improves the analog performance in terms of transconductance, device efficiency, output resistance, and gain. Moreover, linearity figure of merits are also enhanced at lower gate bias in TGRC MOSFET in comparison to conventional and Conventional Recessed Channel (CRC) MOSFET due to reduced harmonic distortions (gm3). Thus, the improved analog and linearity performance at 5 nm NJD and 20 nm LG of TGRC-MOSFET makes it suitable for low power linear RF amplifiers as a nano-scaled device. Thus, these results would serve as a worthy design tool for low power and high performance CMOS circuits.

A linear 60 GHz 65 nm-CMOS power amplifier realization and characterization for OFDM signal

A millimeter-wave Power Amplifier (PA) based on a 65nm CMOS technology from STMicroelectronics has been designed. The targeted feature is the unlicensed band around 60 GHz suitable for wireless personal area network application (WPAN). To optimize the linearity, the PA is designed under class A biasing to have an output compression point (OCP1) close to its saturated Power (P sat). S-parameters and large signal measurement results are demonstrated and compared with electromagnetic simulations. The PA offers a P sat of 8.3 dBm, an OCP1 of 6 dBm and a gain of 6.7 dB. The die area is 0.29 mm2 with pads. Considering those results, one-tone simulations are not sufficient to characterize the linearity performances of the PA in its real conditions of use. Consequently, two-tone simulations are firstly performed. After, linearity figures of merit (FoM) are discussed applying an orthogonal frequency-division multiplexing (OFDM) modulated signal. The PA offers an adjacent channel power ratio (ACPR) of 15 dB and an error vector magnitude (EVM) of 20% at PA compression operating mode.

High-Current Photodetectors as Efficient, Linear, and High-Power RF Output Stages

Recent progress in high-current photodiodes now makes it possible to efficiently generate over 26 dBm of RF power directly from the output of a photodiode. This paper describes two photodetector designs which demonstrate excellent large- and small-signal behavior. Maximum small-signal compression currents have increased to over 700 mA at 300 MHz. Output RF power amplifier stage efficiencies of over 45% (class AB operation) and 35% (class A) have been achieved from 0.3 to 6 GHz with RF power outputs over 26 dBm. The linearity figure of merit (LFOM) is also shown to be greater than 50, leading to the possibility of implementing very high linearity RF power amplifiers in the future.

AM-to-PM Transfer as Reflection of Phase Concavity

Modern communications systems that involve nonlinear, high-power amplifiers, and linearizers typically have many specifications on linearity, including nonlinear phase shift, amplitude modulation-to-phase modulation (AM-to-PM) conversion, carrier-to-third-order-intermodulation (C/3IM) separation, noise power ratio (NPR), and AM-to-PM transfer. For large(ges10 db) carrier separations and high gain linearity, we demonstrate that AM-to-PM transfer in traveling-wave tube amplifiers is approximately proportional to the second derivative of the RF phase versus input drive curve (phase concavity), with a negligible contribution from phase slope. The validity of this approximation improves as the amplifier transfer characteristic approaches that of an ideal limiter. This result allows insight into the AM-to-PM transfer behavior and prediction of the metric with minimal computation. This also allows one to more easily understand the trades involved when optimizing between AM-to-PM transfer and other linearity figures of merit (such as C/3IM).

The voltage-dependent IP3 performance of a 35-GHz InAlAs/InGaAs-InP HBT amplifier

Here we report on the first IP3 results of a 35-GHz Ka-band amplifier based on InAlAs/InGaAs-InP heterofunction bipolar transistors (HBT's). The amplifier combines four 1×10 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> quad-emitter HBT devices for a total emitter area of 160 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> to achieve a gain of 5 dB and an IP3 of 26.5 dBm at 35 GHz. IP3 was characterized over collector bias voltage and indicates that there is an optimum V/sub ce/, corresponding to a maximum IP3 to DC power ratio, which is related to the HBT nonlinear voltage-dependent collector-base capacitance. A maximum IP3-to-DC power linearity figure of merit (LFOM) of 4.1 is achieved at a total collector current of 48 mA and a low V/sub ce/ of 2.25 V, This LFOM is comparable to HEMT's at these frequencies and is expected to improve with the maturity of InAlAs/InGaAs-InP HBT technology.

Ultralinear double pulse doped AlInAs/GaInAs/InP HEMTs

Highly linear InP-based HEMTs have been obtained for the first time by optimising the pulse profile of a double pulse doped AlInAs/GaInAs/InP layer structure. The two-tone measurements performed at f/sub 1/=4.5 GHz and f/sub 2/=4.51 GHz yielded a third-order intercept (IP3) of 31.5 dBm on a 50 /spl mu/m-wide InP HEMT device. The linearity figure of merit (LFOM), defined as IP3/P/sub dc/, was 41.