Abstract
A new hetero-structure vertical tunnel field effect transistor is proposed and investigated using Sentaurus Technology Computer-aided Design simulation. Since the direction of the gate electric field is in alignment with the direction of tunneling of electrons, a higher on state current is attained. Optimization of the geometric dimension of the proposed structure is carried out to yield its optimum performance. As temperature variation affects the device performance, temperature analysis of the proposed structure is performed in which both the off state leakage current and the average subthreshold swing increases with temperature. Further investigation on the influence of temperature variation is carried out in terms of Analog/RF parameters such as transconductance, gate capacitance, cut-off frequency, transconductance frequency product and linearity figure of merits. It is observed that the proposed structure attains superior linearity performance and lower distortion at higher gate voltage with rise in temperature and is less affected by temperature variation at lower gate voltage.
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