Transistor Leakage Research Articles

On the Origin of Thermal Runaway in a Trench Power MOSFET

In this paper, we investigate the origin of thermal runaway in the trench power MOSFET of a modern smart power IC technology. Experimental data on the temperature rise during power pulses show that the onset of thermal runaway depends on the biasing condition even if the power pulses have equal power dissipation. The beginning of thermal runaway in this work is denoted by the inflection point in the measured temperature data. For the experimental data points, the onset varies from 340 °C to 520 °C. Comparison of these experimental data with an analysis based on the stability factor shows very good agreement. The stability factor analysis demonstrates that, above the temperature compensation point (TCP), the driving force for thermal runaway is the thermally generated leakage current of the parasitic n-p-n bipolar transistor. The decrease of mobility and, hence, the MOS channel current above the TCP stabilizes the power MOSFET. In contrast, below the TCP, both the increase of the MOS channel current and the parasitic n-p-n bipolar transistor leakage current with temperature contribute to the thermal runaway.

Reduction of Power Dissipation in Logic Circuits

The most research on the power consumption of circuits has been concentrated on the switching power and the power dissipated by the leakage current has been relatively minor area. In today‟s IC design, one of the key challenges is the increase in power dissipation of the circuit which in turn shortens the service time of battery-powered electronics, reduces the longterm reliability of circuits due to temperature-induced accelerated device and interconnects aging processes, and increases the cooling and packaging costs of these circuits. In this paper the main aim is to reduce power dissipation. A new design method for various logical circuits design, which is low power, compared to general Static CMOS logic. In this technique both NMOS transistor and PMOS transistors in various logic circuits is split into two transistors. Leakage current flowing through the NMOS transistor stack reduces due to the increase in the source to substrate voltage in the top NMOS transistor and also due to an increase in the drain to source voltage in the bottom NMOS transistor Leakage current flowing through the PMOS transistor stack reduces due to the increase in the source to substrate voltage in the top PMOS transistor and also due to an increase in the drain to source voltage in the bottom NMOS transistor. The tool used is TANNER EDA for schematic simulation. The simulation technology used is MOSIS 180nm.

Low Gate-Induced Drain Leakage and Its Physical Origins in Si Nanowire Transistors

Gate-induced drain leakage (GIDL) in Si nanowire transistors fabricated on silicon-on-insulator substrates is systematically studied. In narrow nanowire transistors, GIDL current is obtained by relatively small potential difference between the gate and the drain due to the superior electrostatic control by gate voltage. On the other hand, variation of GIDL current with gate voltage is drastically reduced in nanowire transistors with the wire width of around 10 nm, which realizes devices with extremely small off-current. The reduction of local electric field around the drain junction due to low impurity concentration in source/drain extensions and the relatively large source/drain parasitic resistance are identified as the main mechanisms of small GIDL current.

A 600kHz to 1.2GHz all-digital delay-locked loop in 65nm CMOS technology

This paper presents an ultra-wide-range all-digital delay-locked loop (DLL). The proposed DLL uses a novel delay circuit which uses the transistor's leakage current in advanced CMOS process to generate a very large propagation delay. Thus, the proposed DLL can operate at very low frequency with small chip area and low power consumption. The proposed DLL can operate from 600kHz to 1.2GHz in the typical case. The power consumption of the DLL is 2.6mW at 1.2GHz and 0.366mW at 600kHz with 1.0V power supply. The measured r.m.s jitter and peak-to-peak jitter at 1.2GHz are 3.38ps and 39.29ps, respectively.

A Novel Body Bias Selection Scheme for Leakage Minimization

In this letter, a novel body bias selection scheme for minimizing the leakage of MOS transistors is presented. The proposed scheme directly monitors leakages at present and adjacent body bias voltages, and dynamically updates the voltage at which the leakage is minimized regardless of process and temperature variations. Comparison results in a 46nm CMOS technology indicated that the proposed scheme achieved leakage reductions of up to 68% as compared to conventional body biasing schemes.

Response of a 0.25 μm thin-film silicon-on-sapphire CMOS technology to total ionizing dose

The radiation response of a 0.25 μm silicon-on-sapphire CMOS technology is characterized at the transistor and circuit levels utilizing both standard and enclosed layout devices. The threshold-voltage shift is less than 170 mV and the leakage-current increase is less than 1 nA for individual standard-layout nMOSFET and pMOSFET devices at a total dose of 100 krad(SiO2). The increase in power supply current at the circuit level was less than 5%, consistent with the small change in off-state transistor leakage current. The technology exhibits good characteristics for use in the electronics of the ATLAS experiment at the Large Hadron Collider.

A comparative study on gate leakage and performance of high-𝛋 nano-CMOS logic gates

This paper provides a novel attempt to evaluate the gate leakage and delay characteristics of CMOS transistors and logic gates with various alternative high-κ gate dielectrics, which are replacing SiO2 in traditional nanoscale MOSFETs. Results have been obtained for both fixed as well as variable loads. The assumption that all gates drive the same load is considered in order to provide a fair comparison of the effect of the variation of design and process parameters, especially that of different high-κ dielectrics on the gate direct tunnelling current and propagation delay. On the other hand, the variable loading effect considers a set of practical loading conditions for the logic gates. An exhaustive comparison of all cases finally presents concluding evidence that the tunnelling current is independent of the loading conditions. On the other hand, there is an increase in the delay as the dielectric constant of the gate material, and consequently the load on the device, increases. Ultimately, this paper presents fast and accurate models for on-the-fly calculation of tunnelling current and delay with the aim of integrating them into design automation tools.

Production, Characterization and Application of Silicon-on-Sapphire Wafers

Silicon-on-sapphire (SOS) thin film systems have had specific electronic applications because they can reduce noise and current leakage in metal oxide semiconductor transistors. However, there are some issues in producing defect-free SOS wafers. Dislocations, misfit, micro twins and residual stresses can emerge during the SOS processing and they will reduce the performance of an SOS product. For some reasons, research publications on SOS in the literature are not extensive, and as a result, the information available in the public domain is fragmentary. This paper aims to review the subject matter in an as complete as possible manner based on the published information about the production, characterization and application of SOS wafers.

Characteristics analysis and optimization design of a new ESD power clamp circuit

As CMOS technology scales down, the design of ESD protection circuits becomes more challenging. There are some disadvantages for the actual power clamp circuit. In this paper, an optimization ESD power clamp circuit is proposed. The new clamp circuit adopts the edge triggering True Single Phase Clocked Logic (TSPCL) D flip-flop to turn on and time delay, it has the advantage of dynamic transmission structure. By adding a leakage transistor of small size, the clamp circuit can turn off effectively. By changing the W/ L ratio, the clamp can safely protect the gate of ESD power clamp devices from thermoelectric breakdown. The results show that the circuit can reduce the false triggering and power supply noise more effectively, it can be widely used in high-speed integrated circuits. The proposed structure has the advantages of low power and low cost, and can be used to the system-level ESD protection.

Dual-Source-Line-Bias Scheme to Improve the Read Margin and Sensing Accuracy of STTRAM in Sub-90-nm Nodes

This brief analyzes the circuit-induced challenges to reliability and write current scaling of spin-torque-transfer random access memory (STTRAM). We show that, at sub-90-nm nodes, increased transistor leakage increases the probability of incorrect sensing requiring a higher read current. However, a higher read current can increase the read disturb failure, particularly with a reduced write current. To satisfy the conflicting requirements of read margin and sensing accuracy, we propose a source-line biasing technique. Simulations in predictive 65-nm nodes show that the proposed solution simultaneously reduce the sensing errors and improve the read margin.

High-Efficiency Differential-Drive CMOS Rectifier for UHF RFIDs

A high-efficiency CMOS rectifier circuit for UHF RFIDs was developed. The rectifier has a cross-coupled bridge configuration and is driven by a differential RF input. A differential-drive active gate bias mechanism simultaneously enables both low ON-resistance and small reverse leakage of diode-connected MOS transistors, resulting in large power conversion efficiency (PCE), especially under small RF input power conditions. A test circuit of the proposed differential-drive rectifier was fabricated with 0.18 mu m CMOS technology, and the measured performance was compared with those of other types of rectifiers. Dependence of the PCE on the input RF signal frequency, output loading conditions and transistor sizing was also evaluated. At the single-stage configuration, 67.5% of PCE was achieved under conditions of 953 MHz, - 12.5 dBm RF input and 10 KOmega output load. This is twice as large as that of the state-of-the-art rectifier circuit. The peak PCE increases with a decrease in operation frequency and with an increase in output load resistance. In addition, experimental results show the existence of an optimum transistor size in accordance with the output loading conditions. The multi-stage configuration for larger output DC voltage is also presented.

Measurement and Analysis of Variability in 45 nm Strained-Si CMOS Technology

A test-chip in a low-power 45 nm technology, featuring uniaxial strained-Si, has been built to study variability in CMOS circuits. Systematic layout-induced variation, die-to-die (D2D), wafer-to-wafer (W2W) and within-die (WID) variability has been measured over multiple wafers, analyzed and attributed to likely causes in the manufacturing process. Delay is characterized using an array of ring oscillators and transistor leakage current is measured with an on-chip ADC. The key results link systematic layout-dependent and die-to-die variability as being caused by gate patterning and material strain. In comparison to a previous 90 nm experiment, gate proximity now contributes less to frequency variability, causing a 2% change in overall performance, while strain has increased its contribution to about 5% of the overall performance.

Measurements and Analysis of Process Variability in 90 nm CMOS

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A test chip has been built to study the effects of circuit layout on variability, and to characterize within-die (WID) and die-to-die (D2D) variability of delay and leakage current in 90 nm CMOS technology. Delay is obtained through the measurement of ring oscillator frequencies, and the transistor leakage current is measured by an on-chip analog-to-digital converter (ADC). It has been found that the transistor performance depends strongly on the polysilicon (poly-Si) gate density, and the spatial correlation depends on the gate orientation and the direction of poly-Si spacing. WID variation is small with three standard deviations over a mean <formula formulatype="inline"><tex Notation="TeX">$(3\sigma/\mu)$</tex> </formula> of around 3.5%, whereas D2D and systematic layout-induced variations are significant, with a <formula formulatype="inline"><tex Notation="TeX">$3\sigma/\mu$</tex> </formula> D2D variation of <formula formulatype="inline"><tex Notation="TeX">${\sim}\,$</tex> </formula>15% and a maximum layout-induced frequency shift of 10%. Finally, a set of guidelines is proposed to help circuit designers mitigate the effects of process variations on CMOS performance. </para>

Total dose radiation effects on SOI NMOS transistors with different layouts

Partially-depleted Silicon-On-Insulator Negative Channel Metal Oxide Semiconductor (SOI NMOS) transistors with different layouts are fabricated on radiation hard Separation by IMplanted OXygen (SIMOX) substrate and tested using 10 keV X-ray radiation sources. The radiation performance is characterized by transistor threshold voltage shift and transistor leakage currents as a function of the total dose up to 2.0×106 rad(Si). The results show that the total dose radiation effects on NMOS devices are very sensitive to their layout structures.

94 GHz Voltage Controlled Oscillator With 5.8% Tuning Range in Bulk CMOS

A 94 GHz fundamental mode voltage controlled oscillator (VCO) is demonstrated using low leakage transistors in a 65 nm digital CMOS process with six metal layers. It achieves a tuning range of 5.8% and phase noise of -106 dBc/Hz at 10 MHz offset from a 94.9 GHz carrier. The output power varies between -4 and -8 dBm over the tuning range. The VCO draws 6 mA bias current from a 1.5 V supply and 6 mA from a 0.8 V supply.

TI Low-Leakage130nm Digital Process with Nonvolatile FRAM for Ultra-Low-Power Medical Electronics

Both external and implantable devices are becoming more sophisticated and are requiring more on-chip memory to store data from biological sensors. To deal with this complexity, chip designs are moving toward smaller process geometries, which provide added functionality, reduced size, or both, often along with a reduction in dynamic power. However, leakage power begins to increase significantly at the 130nm node if steps are not taken to mitigate the increased transistor leakage. Lower operating voltages and careful transistor design can offset some of this increase. These very changes, however, make it difficult to design a dense, stable low-power SRAM. Nonvolatile memories like FRAM (F-RAM) avoid these difficulties and save power by simply turning off the memory when not in use. This is particularly valuable since many medical devices have very low duty cycle. FRAM provides the added benefit of providing SRAM-like active power, unlike competing nonvolatile technologies. To meet the challenging power requirements of medical devices, a new ultra-low-power 130nm process has been developed. The new process includes a very-high-density, SER-resistant, nonvolatile FRAM and an ultra-low-leakage transistor, coupled with a library that is optimized for low-power operation. This paper compares the power, area and performance of competing process technologies for a typical implantable medical design and highlights the advantages that FRAM provides in low static power through a transparent power-down capability and in low SRAM-like active power.

New non‐volatile logic based on spin‐MTJ

AbstractAs the minimum dimensions of complementary metal oxide semiconductor (CMOS) transistors shrink down to 90 nm and below, some physical obstacles have been observed which prevent rigidly this miniaturization. For example, high transistor leakage currents lead to an important increase of the ‘idle’ power consumption of CMOS memory arrays. Many nanodevices are therefore the subject of research and development to help CMOS technology continue to downscale by Moore's law. Among them, the magnetic tunnel junction (MTJ) is one of the most promising candidates, because its non‐volatility offers the possibility to power off the chip to greatly reduce the ‘idle’ energy dissipation of conventional CMOS circuits. Moreover, its resistance value property (several kΩ), compatible with CMOS transistor conductivity, allows its states to be sensed easily with CMOS circuits. The novel spin transfer torque (STT) writing approach, which has been recently introduced and developed, reduces significantly the switching energy and data disturbance when compared with the conventional MTJ writing approach. It makes the MTJ technology much more suitable than other nanodevices for commercial applications. In this paper, hybrid STT‐based MTJ (spin‐MTJ)/CMOS logic circuits and some design techniques are proposed based on STMicroelectronics 90 nm CMOS technology and the published Hitachi spin‐MTJ technology. A first prototype has been simulated and evaluated. (© 2008 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Planar split dual gate MOSFET

A new planar split dual gate (PSDG) MOSFET device, its characteristics and experimental results, as well as the three dimensional device simulations, are reported here for the first time. Both theoretical calculation and 3D simulation, as well as the experiment data, show that the two independent split dual gates can provide dynamical control of the device characteristics, such as threshold voltage (Vt) and sub-threshold swing (SS), as well as the device saturated current. The PSDG MOSFET transistor leakage current (Ioff) can be reduced as much as 78% of the traditional single gate MOSFET. The PSDG is fabricated and fully compatible with our conventional 0.18 μm logic process flow.

The Effects of Mechanical Uniaxial Stress on Junction Leakage in Nanoscale CMOSFETs

This paper reports the influences of uniaxial mechanical stress on the reverse-biased source/drain to substrate junction leakage of state-of-the-art 65 nm CMOS transistors. For n-channel metal-oxide-semiconductor (NMOS) transistors, the band-to-band tunneling (BTBT) dominates the junction leakage current due to heavily doped junction and pocket implants. However, for p-channel metal-oxide-semiconductor (PMOS) transistors with embedded SiGe source/drain, the leakage current is found to result from both BTBT and generation current due to defects generated in the SiGe layer and at the SiGe/Si interface. A four-point bending technique is used to apply mechanical uniaxial stress on NMOS and PMOS devices along the longitudinal direction. It was found that the leakage current of both devices increases (decreases) with applied uniaxial compressive (tensile) stress, and that the strain sensitivity of the junction leakage of NMOS transistors is much weaker than that of PMOS transistors. By combining the bending technique with process strained Si (PSS) technology, additional stress was applied to NMOS and PMOS with high built-in stress to investigate the characteristics of junction leakage under extremely high uniaxial stress. It is shown that uniaxial tensile stress can both enhance the NMOS device performance and decrease the junction leakage. However, for the PMOS, there exists a tradeoff between boosting the transistor performance and decreasing the junction leakage current, so there is a limit in the amount of compressive stress that can be beneficially applied.

N-polar GaN∕AlGaN∕GaN high electron mobility transistors

We describe the development of N-polar GaN-based high electron mobility transistors grown by N2 plasma-assisted molecular beam epitaxy on C-face SiC substrates. High mobility AlGaN∕GaN modulation-doped two-dimensional electron gas channels were grown, and transistors with excellent dc and small-signal performance were fabricated on these wafers. Large-signal dispersion was observed, and the trap states responsible for this were identified, and layer designs to remove the dispersive effects of these traps were demonstrated. Finally, an AlGaN-cap layer was used to reduce gate leakage in these devices, and a low-dispersion high breakdown voltage device was achieved. This detailed study of dispersion and leakage in N-polar GaN-based transistors establishes a technological base for further development of field effect devices based on N-polar III-nitrides.