Transistor Leakage Research Articles

Source/drain extension asymmetric counter-doping for suppressing channel leakage in stacked nanosheet transistors

In the relentless pursuit of semiconductor device scaling, stacked silicon nanosheet gate-all-around field-effect transistors (NSFETs) are emerging as key candidates for sub-3nm technology nodes. However, the challenge of channel leakage in these devices is critical and necessitates innovative solutions. A novel SDE asymmetric counter-doping technique is proposed in this study. It investigates the impact of source/drain extension on device performance using different process schemes through three-dimensional technical computer-aided design (3D TCAD) simulations. The simulations demonstrate a comprehensive technically advantages for 25.2 %/16.65 % reduction in the off-state leakage, 27.36 %/15.03 % improvement in the on-off current ratio of N/P NSFETs, respectively. Furthermore, it shows more performance gain as the gate length scaling beyond 3 nm technology nodes. The compatibility of the asymmetric counter-doping method with mainstream NSFET integration flows and its scalability to 10 nm gate lengths indicate that it is a promising approach to optimize NSFETs performance with little extra process cost.

A 275 pW, 0.5 V supply insensitive gate-leakage based current/voltage reference circuit for a wide temperature range of −55 to 100 °C without using amplifiers and resistors

The paper presents a 0.5 V, ultra-low power current, and voltage reference circuit in a single block, giving reference values of 90.7 pA and 288 mV. The proposed block uses proper addition of CTAT and PTAT curves, resulting in an excellent temperature coefficient of 15.2 ppm/°C and 36.8 ppm/°C for compensated current and voltage values, respectively, at a nominal supply of 0.5 V for a wide temperature range of −55 °C to 100 °C. Usage of gate leakage transistors in place of resistors helps in reducing the power and area of the circuit to 0.087 mm2. The circuit is implemented in 90 nm technology and operates effectively across a wide voltage range of 0.5 V–2.6 V with a supply sensitivity of 0.028 %/V and 0.154 %/V for current and voltage reference, respectively. The entire circuit takes a power of 275.26 pW at nominal conditions.

A 8.1-nW, 4.22-kHz, −40–85 °C relaxation oscillator with subthreshold leakage current compensation and forward body bias buffer for low power IoT applications

This paper presents a relaxation oscillator (RxO) utilizing subthreshold transistor leakage current compensation (SLC) technology to expand the operating range from 70 °C to 85 °C at high temperatures. The compensated RxO outperforms the uncompensated counterpart by 25 times for temperature coefficient (TC). Additionally, forward body bias (FBB) technology optimizes the digital buffer delay with temperature drift at low supply voltage, extending the oscillator’s low-temperature range from −20 °C to −40 °C. Fabricated in a 65 nm CMOS process, the oscillator consumes a mere 8.1 nW at a 0.4 V supply voltage. At room temperature, it operates at 4.22 kHz with an energy efficiency of 1.92 nW/kHz. The oscillator demonstrates a temperature coefficient (TC) of 114.01 ppm/°C within the range of −40 °C to 85 °C, rendering it a prospective choice for low-power Internet of Things (IoT) applications.

Micromechanical mode-localized electric current sensor

This paper outlines the design of a novel mode-localized electric current sensor based on a mechanically sensitive element of weakly coupled resonator systems. With the advantage of a high voltage sensitivity of weakly coupled resonator systems, the current under test is converted to voltage via a silicon shunt resistor, which causes stiffness perturbation to one resonator. The mode-localization phenomenon alters the energy distribution in the weakly coupled resonator system. A theoretical model of current sensing is established, and the performance of the current sensor is determined: the sensitivity of the electric current sensor is 567/A, the noise floor is 69.3 nA/√Hz, the resolution is 183.6 nA, and the bias instability is 81.6 nA. The mode-localized electric current sensor provides a new approach for measuring sub-microampere currents for applications in nuclear physics, including for photocurrent signals and transistor leakage currents. It could also become a key component of a portable mode-localized multimeter when combined with a mode-localized voltmeter. In addition, it has the potential for use in studying sensor arrays to achieve higher resolution.

A SMART DESIGN OF A MULTI-DIMENSIONAL ANTENNA TO ENHANCE THE MAXIMUM SIGNAL CLUTCH TO THE ALLOWABLE STANDARDS IN 5G COMMUNICATION NETWORKS

At the current deep submicron and nanometer level, the leakage power is becoming the major contributor to overall power consumption in modern VLSI circuits. This research paper presents a novel approach to reducing leakage power by inserting two leakage transistors in the middle of pull-down and pull-up paths. Out of these two leakage transistors, one is the PMOS transistor, and another one is the NMOS transistor. This research work presents a dynamic CMOS inverter and 6T SRAM cell with and without transmission gate (TG) to reduce leakage power using the LECTOR and LECTOR-B techniques. The Cadence Virtuoso simulation tool is used to presents the results in terms of static power. Using the 45-nm technology node, the performance in terms of static power is analyzed. It is observed that using LECTOR and LECTOR-B techniques, the overall reduction in static power is 26% and 20%, respectively, compared to the conventional design for SRAM cell. Similar improvements are also noted for dynamic CMOS inverter and TG SRAM cell. Since the operating range of 5G communication networks is the same as that of the previous generation, there are no difficulties in using these antennas on 5G communication networks. For any technology, the use of antennas makes it possible to bring data rates closer to maximum values. The new technology that uses separate receivers and transmitters on the same frequency band has further increased the speed of receiving and transmitting data. The design of the existing 4G modem provides for the use of antenna technology. The proposed model provides the construction of a multidimensional antenna. The other passive devices it has a one-way direction, which increases the received signal and reduces the amount of interference from the sides to the back. Therefore, the proposed model possible to increase the signal level to acceptable values, even at unstable reception levels thereby increasing the speed of receiving and transmitting the information. The undoubted advantage of panel antennas is their low cost and exceptional reliability. There is practically nothing in the design that can be broken even when falling from a great height. The only weak point is the high-frequency cable, which can break at the point where it enters the case. To extend the life of the device, the cable must be securely connected.

Reducing the Effect of Carry Propagation on Spintronic Adders

Due to the exponential increase of transistor leakage currents, especially in the technologies lower than 90[Formula: see text]nm, the static power consumption has dramatically increased. So, it is regarded as one of the main problems of the CMOS circuits. The spintronic devices, such as magnetic tunnel junction (MTJ), have notable advantages including low-static power consumption, nonvolatility, high endurance, compatibility with the CMOS transistors and the possibility of fabrication in high scales. Hence, the hybrid MTJ/CMOS circuits are considerable options to mitigate the problem of high-static power consumption in CMOS circuits. In this paper, a nonvolatile and low-power hybrid MTJ/CMOS full adder is proposed for implementation of in-memory computing. The drawback of existing full adders is their low-speed and high-power consuming for MTJ switching, which terribly affect the performance of multi-bit adders using these full adders. In this work, a new full adder is designed by eliminating the MTJ and transistor related to the input carry bit and modifying the tree structure of the MTJ network associated with the other inputs. In the proposed full adder, the effect of carry propagation has drastically decreased and its power consumption is also improved.

Oxide electronics: Translating materials science from lab-to-fab

Advances in the science and technology of thin-film materials have fueled a myriad of developments in large area electronics. This is particularly true for amorphous oxide semiconductors. Oxides have underpinned a number of technologically significant innovations in displays, sensors, and photovoltaics. Now they are setting the stage for exciting new applications related to flexible electronics and three-dimensional (3D) integration for post-complementary metal oxide semiconductor (CMOS) back-end-of-line processing in the quest for more-than-Moore solutions. This article reviews the development of oxide semiconductors and associated integration processes that have translated materials science fiction to commercial reality on a large scale. These advances have been driven by a host of advantages such as low cost, prudent manufacturing and large area scalability. What makes oxide semiconductors so attractive? These materials have a wide bandgap, which provides for high transparency; a cool feature for seamless embedding of electronics, particularly displays and imagers, for the immersive ambient. The OFF-current in oxide thin-film transistors is ultralow, thanks to the very low density of states in the bandgap. Indeed, this attribute is indispensable to minimize charge leakage in switching transistors and for low power, low-voltage, high-resolution sensor interfaces. More importantly, oxide thin-film transistors can be processed at relatively low temperatures thus making them amenable for 3D integration on post-processed CMOS silicon. This article provides the current status of the oxide semiconductor technology. We review the evolution of oxides based on their functional properties, along with deposition and solution processing techniques for heterostructure thin-film transistors, phototransistors, nanowire image sensors, ultralow power Schottky-barrier transistors, and 3D integration for back-end-of-line CMOS. These devices constitute fundamental building blocks for a new generation of applications ranging from interactive displays and imaging to future 3D electronic systems that are not constrained by form factor.Graphical abstract

Measurement and Evaluation of the Within-Wafer TID Response Variability on BOX Layer of SOI Technology

Within-wafer total ionizing dose (TID) response variability on buried oxide (BOX) layer of silicon-on-insulator (SOI) technology is investigated in this article. TID response variability is measured by the threshold voltage and OFF-state leakage of transistors evenly distributed on the wafer locations. Experimental results show the larger standard deviation of threshold voltage and OFF-state leakage distribution for irradiated devices than unirradiated devices, illustrating the within-wafer TID response variability. The hole traps variation in the BOX layer is responsible for the within-wafer TID response variability of SOI technology. Moreover, a data analysis method according to T-distribution is proposed to obtain the within-wafer TID response variability by the sampling testing results of limited wafer locations. Our data show that the T-distribution method is reasonable to assess the TID-induced variability of a process when only a few samples are available.

A comparative study of integrated RF to DC power conversion system for RF energy harvesting

Battery power has been a popular choice of delivering DC power to many portable RF systems including wireless sensor nodes/internet of Everything (IoE). An autonomously powered RF system of the orders of 100’s of µwatts is becoming increasingly popular in recent times because of integrated solutions in energy harvesting. The minimum sensitivity of an RF energy harvester and the targeted deliverable output voltage for a specific load resistance are dictated by threshold voltage of transistors used and reverse leakage of such transistors. A detailed look into the architectures of rectifiers can help tackle design problems in the RF-DC conversion process. So in this work we focused on the design of integrated RF energy harvesting by studying four important architectures of RF-DC converters. To achieve a fair comparison between these architectures, a matching network operating at 0.8 MHz is designed and applied for simulation. All of these converters are tested in LT-SPICE XVII using the same designed matching network and the rectifiers are implemented in 180 nm CMOS technology.

Low-Cutoff Frequency Reduction in Neural Amplifiers: Analysis and Implementation in CMOS 65 nm.

Scaling down technology demotes the parameters of AC-coupled neural amplifiers, such as increasing the low-cutoff frequency due to the short-channel effects. To improve the low-cutoff frequency, one solution is to increase the feedback capacitors' value. This solution is not desirable, as the input capacitors have to be increased to maintain the same gain, which increases the area and decreases the input impedance of the neural amplifier. We analytically analyze the small-signal behavior of the neural amplifier and prove that the main reason for the increase of the low-cutoff frequency in advanced CMOS technologies is the reduction of the input resistance of the operational transconductance amplifier (OTA). We also show that the reduction of the input resistance of the OTA is due to the increase in the gate oxide leakage in the input transistors. In this paper, we explore this fact and propose two solutions to reduce the low-cutoff frequency without increasing the value of the feedback capacitor. The first solution is performed by only simulation and is called cross-coupled positive feedback that uses pseudoresistors to provide a negative resistance to increase the input resistance of the OTA. As an advantage, only standard CMOS transistors are used in this method. Simulation results show that a low-cutoff frequency of 1.5 Hz is achieved while the midband gain is 30.4 dB at 1 V. In addition, the power consumption is 0.6 μW. In the second method, we utilize thick-oxide MOS transistors in the input differential pair of the OTA. We designed and fabricated the second method in the 65 nm TSMC CMOS process. Measured results are obtained by in vitro recordings on slices of mouse brainstem. The measurement results show that the bandwidth is between 2 Hz and 5.6 kHz. The neural amplifier has 34.3 dB voltage gain in midband and consumes 3.63 μW at 1 V power supply. The measurement results show an input-referred noise of 6.1 μVrms and occupy 0.04 mm2 silicon area.

20 Years of reconfigurable field-effect transistors: From concepts to future applications

The reconfigurable field-effect transistor (RFET), is an electronic device whose conduction mechanism can be reversibly reconfigured between n-type and p-type operation modes. To enable this functionality, those devices do not rely on chemical doping caused by impurities but rather on electrostatic doping, i.e. the generation of mobile carriers via an external potential. This functionality has been first concieved in the early 2000s to reduce the source-drain leakage in ambipolar thin film transistors. Over the years many different concepts have been developed employing different conduction mechanisms as well as channel materials, such as silicon nanowires, carbon nanotubes or two-dimensional layered materials. In addition the focus the research shifted more and more towards the circuit level, bringing the unique device characteristics to fruitation. In this work, we will give an historic overview of the main development phases including thier key-achievements starting from the earlier years reaching untill today. Further, we discuss the most interesting circuit properties arising from the device functionality and summarize the broad range of their potential future applications.

Leakage reduction in dual mode logic through gated leakage transistors

This contribution proposes a technique for leakage power reduction in Dual Mode Logic (DML) circuits by incorporating Gated Leakage Transistor (GLT). The resulting circuits are named as GALEOR with Dual Mode Logic (GDML). Further, GDML design is extended by including a footed diode transistor, the design so obtained is referred to as GALEOR with Dual Mode Logic with footed diode (GDMLD). The analysis is done using footed type A and type B DML gates, resulting in GDML and GDMLD variants referred to as GDML-TA, GDML-TB, GDMLD-TA and GDMLD-TB. Two input NAND and NOR gates along with a full adder and a 2-bit multiplier circuit are used to investigate the proposed techniques at 90 nm and 45 nm technology nodes in both static and dynamic mode using SymicaDE tool. Analysis of leakage power reveals that its value increases with technology scaling. Average leakage power saving is 44.69%-74.11% for GDML and 67.18%-90.76% for GDMLD in static mode. Similarly, in pre-charge phase of dynamic mode, this value varies from 5.47%-28.22% for GDML and 14.55%-77.51% for GDMLD. For evaluation phase, average leakage power saving of 44.69%-74.11% for GDML and 67.18%-90.76% for GDMLD is achieved. Analysis of delay reveals that both the techniques increase delay of the design while providing significant leakage power saving.

Certain investigations in achieving low power dissipation for SRAM cell

The modern semiconductor industry is evolving quite rapidly. Portable and mobile devices are becoming smaller every day and there is also a growing demand for longer battery power. With these demands it is important for researchers to focus on the leakage power in stand-by mode. The SRAM was designed to accurately communicate with CPU, DSP, processor and low-power applications, such as battery-life handheld devices. For some days now, the design engineer focuses mainly on the production of large-capacity memories, high bandwidth and low energy consuming memories. Memory is an integral part of most of these systems and is also diminished as the scale of the system reduces. Low power and processing architecture at high speed is therefore a major concern. The durability of random static access memory cells (SRAM) is another critical factor. This Paper Describes the SRAM architecture designed for the reduction of power consumption or power leakages using sleep transistor and MTCMOS (Multi-Threshold Complementary Metal Oxide Semiconductor) techniques. This helps in the reduction of the CMOS transistor leakages. This paper incorporates multiple threshold strategies to give the proposed high speed, increased reliability and low leakage current of the updated 8T SRAM cell in stand-by memory cell mode. Based on the parameters like power dissipation at a different temperature, read voltage, write voltage, read delay, write delay, compared to the previously designed SRAM architecture of 6T, 7T, 8T and 13T we get low power consumption in our designed 8T SRAM architecture. The simulations are conducted with the UMC 55 nm technology Cadence Virtuoso method.

Enhanced Low-Neutron-Flux Sensitivity Effect in Boron-Doped Silicon.

Space particle irradiation produces ionization damage and displacement damage in semiconductor devices. The enhanced low dose rate sensitivity (ELDRS) effect caused by ionization damage has attracted wide attention. However, the enhanced low-particle-flux sensitivity effect and its induction mechanism by displacement damage are controversial. In this paper, the enhanced low-neutron-flux sensitivity (ELNFS) effect in Boron-doped silicon and the relationship between the ELNFS effect and doping concentration are further explored. Boron-doped silicon is sensitive to neutron flux and ELNFS effect could be greatly reduced by increasing the doping concentration in the flux range of 5 × 109–5 × 1010 n cm−2 s−1. The simulation based on the theory of diffusion-limited reactions indicated that the ELNFS in boron-doped silicon might be caused by the difference in the concentration of remaining vacancy-related defects (Vr) under different neutron fluxes. The ELNFS effect in silicon becomes obvious when the (Vr) is close to the boron doping concentration and decreased with the increase in boron doping concentration due to the remaining vacancy-related defects being covered. These conclusions are confirmed by the p+-n-p Si-based bipolar transistors since the ELNFS effect in the low doping silicon increased the reverse leakage of the bipolar transistors and the common-emitter current gain (β) dominated by highly doped silicon remained unchanged with the decrease in the neutron flux. Our work demonstrates that the ELNFS effect in boron-doped silicon can be well explained by noise diagnostic analysis together with electrical methods and simulation, which thus provide the basis for detecting the enhanced low-particle-flux damage effect in other semiconductor materials.

Multi-mode nanoFETs: From low power to high performance on demand

Dynamic power management at the lowest design level of electronic hardware, i.e. at the device or transistor level, is still a novelty. Instead, energy saving is usually achieved at the circuit level by switching off high performance components and activating low leakage transistors in the current paths. We discuss here performance projections of field-effect transistors providing multiple power modes. A multi-mode (mm) FET can be configured from GHz performance to ultralow leakage by adjusting the charge injection into the transistor channel between thermionic and band-to-band tunnel injection. Nanodevices with ultrathin doping-free channels are the enabler of this novel device concept that requires excellent electrostatic control of the charge type and density. Moreover, nanomaterials with charge carriers of low effective mass will improve the mode tuning of mmFETs. TCAD simulations show that the device current can be switched through nine orders of magnitude at a supply voltage of . The mmFET can also operate in a low dynamic power mode with reduced drive currents but delay times that still allow sub-MHz operation. These properties make mmFETs a promising technology for low power circuitry supplied only by energy harvesters. The possibility to further decrease the supply voltage by integrating a ferroelectric layer in the capacitor stack is also addressed.

Voltage Reference With Linear-Temperature-Dependent Power Consumption

This article presents a novel pico-watt voltage reference (VR) circuit whose power consumption is well controlled at high temperature. Unlike a traditional pico-watt VR circuit whose power consumption increases exponentially with temperature, the power consumption in this article increases linearly with temperature, thus saving much energy at high temperature. It generates the reference voltage through a 2-transistor (2-T) structure and a current generator to well control the current versus temperature. In the current generator, a gate leakage transistor replaces a huge resistor, thus saving 4-mm2 area. Fabricated in a 0.13- $\mu \text{m}$ CMOS process, this VR circuit generates a reference voltage of about 560 mV and shows an average temperature coefficient (TC) of 18.4 ppm/°C after trimming across −25 °C to 85 °C and a line sensitivity (LS) of 0.15%/V, while consuming 20 pW at 1-V ${V} _{\text {DD}}$ and 27 °C. The power consumption at 3.3-V ${V} _{\text {DD}}$ and 85 °C is 114 pW, which is at least two times smaller than reported in state-of-the-art work at high temperature. The core area is 0.003 mm2.

Nanoelectromechanical relay without pull-in instability for high-temperature non-volatile memory

Emerging applications such as the Internet-of-Things and more-electric aircraft require electronics with integrated data storage that can operate in extreme temperatures with high energy efficiency. As transistor leakage current increases with temperature, nanoelectromechanical relays have emerged as a promising alternative. However, a reliable and scalable non-volatile relay that retains its state when powered off has not been demonstrated. Part of the challenge is electromechanical pull-in instability, causing the beam to snap in after traversing a section of the airgap. Here we demonstrate an electrostatically actuated nanoelectromechanical relay that eliminates electromechanical pull-in instability without restricting the dynamic range of motion. It has several advantages over conventional electrostatic relays, including low actuation voltages without extreme reduction in critical dimensions and near constant actuation airgap while the device moves, for improved electrostatic control. With this nanoelectromechanical relay we demonstrate the first high-temperature non-volatile relay operation, with over 40 non-volatile cycles at 200 ∘C.

Proposed 3.5 µW CNTFET-MOSFET hybrid CSVCO for power-efficient gigahertz applications

PurposeSeveral ultra-low power and gigahertz current-starved voltage-controlled oscillator (CSVCO) circuits have been proposed and compared here. The presented structures are based on the three-stage hybrid circuit of the carbon nanotube field-effect transistors (CNTFETs) and low-power MOSFETs. The topologies exploit modified and compensated Schmitt trigger comparator parts to demonstrate better consumption power and frequency characteristics. The basic idea in the presented topologies is to compensate the Schmitt trigger comparator part of the basic CSVCO for achieving faster carrier mobility of the holes, reducing transistor leakage current and eliminating dummy transistors.Design/methodology/approachThis study aims to propose and compare three different comparator-based VCOs that have been implemented using the CNTFETs. The considered circuits are shown to be capable of delivering the maximum 35 tuning frequency in the order of 1 GHz to 5 GHz. A major power thirsty part of the high-frequency ring VCOs is the Schmitt trigger stage. Here, several fast and low-power Schmitt trigger topologies are exploited to mitigate the dissipation power and enhance the oscillation frequency.FindingsAs a result of proposed modifications, more than one order of magnitude mitigation in the VCO power consumption with respect to the previously presented three-stage CSVCO is reported here. Thus, a VCO dissipation power of 3.5 µW at the frequency of 1.1 GHz and the tuning range of 26 per cent is observed for the well-established 32 nm technology and the supply voltage of 1 V. Such a low dissipation power is obtained around the operating frequency of the battery-powered cellular phones. In addition, using the p-carrier mobility compensation and enhancing the rise time of the Schmitt trigger part of the CSVCO, a maximum of 2.38 times higher oscillation frequency and 72 per cent wider tuning range with respect to Rahane and Kureshi (2017) are observed. Simultaneously, this topology exhibits an average of 20 per cent reduction in the power consumption.Originality/valueSeveral new VCO topologies are presented here, and it is shown that they can significantly enhance the power dissipation of the GHz CSVCOs.

Simulation and experimental study of FET biosensor to detect polycyclic aromatic hydrocarbons

Abstract In this paper, the DNA/Cu2O-GS nanostructure was simulated to detect polycyclic aromatic hydrocarbons (PAHs) and compared with our experimental results. We use a simulation for calculations based on density functional theory (DFT). In the first step, DNA/Cu2O-GS nanostructure was simulated and adsorption mechanism, the density of states and charge transfer process were investigated in the presence and absence of PAHs using the QUANTUM ESPRESSO software and BoltzTrap computing code. The simulation results showed that Cu2O-GS nanostructure can be well used to adsorption and stabilization of DNA. Also the simulation results of electrical conductivity change showed that DNA/Cu2O-GS nanostructure can be well used as a field effect transistor (FET) to detect PAHs. On the other hand, the electric current changes of the DNA/Cu2O-GS-FET for three samples of PAHs (benzene, toluene, and naphthalene) were experimentally studies. Also current leakage, the sensitivity, and dynamic range of transistor for benzene, naphthalene and toluene experimentally were investigated. The experimental results show that the DNA/Cu2O-GS-FET can use as a biosensor for PAHs. Our simulation and experimental results are in good agreement and this DFT-based simulation idea can use for other biosensors.

A Review On Modified Gate Diffusion Input Logic: An Approach For Area And Power Efficient Digital System Design

In recent days, the main motto of VLSI designers is to reduce the power and area as devices are becoming battery-operated, compact and require enhanced functionality and features. Due to the scaling and shrinking of devices, the transistor leakage power has increased at an exponential rate. In this paper, analysis on the research based on the Modified gate diffusion input technique (m-GDI) which has gained much attention in recent days are encompassed. Consequently, 31 research papers homologous to m-GDI technique are assessed and analysed based on the numerous targets. In this review, we present the m-GDI Technique, a low power technique and scrutinize the modern breakthroughs with several pros and cons. The thorough examination is done on finding the inclusion of the issues, methodologies, simulation tools and technologies used.