Leakage reduction in dual mode logic through gated leakage transistors

Abstract

This contribution proposes a technique for leakage power reduction in Dual Mode Logic (DML) circuits by incorporating Gated Leakage Transistor (GLT). The resulting circuits are named as GALEOR with Dual Mode Logic (GDML). Further, GDML design is extended by including a footed diode transistor, the design so obtained is referred to as GALEOR with Dual Mode Logic with footed diode (GDMLD). The analysis is done using footed type A and type B DML gates, resulting in GDML and GDMLD variants referred to as GDML-TA, GDML-TB, GDMLD-TA and GDMLD-TB. Two input NAND and NOR gates along with a full adder and a 2-bit multiplier circuit are used to investigate the proposed techniques at 90 nm and 45 nm technology nodes in both static and dynamic mode using SymicaDE tool. Analysis of leakage power reveals that its value increases with technology scaling. Average leakage power saving is 44.69%-74.11% for GDML and 67.18%-90.76% for GDMLD in static mode. Similarly, in pre-charge phase of dynamic mode, this value varies from 5.47%-28.22% for GDML and 14.55%-77.51% for GDMLD. For evaluation phase, average leakage power saving of 44.69%-74.11% for GDML and 67.18%-90.76% for GDMLD is achieved. Analysis of delay reveals that both the techniques increase delay of the design while providing significant leakage power saving.