Abstract
A logical circuit are either act in static mode or dynamic mode of operation. Recently, a novel dual mode logic (DML) family was proposed. This logic allows a circuit to operate in two modes:1) static 2) dynamic mode. DML gates, which can be switched between these modes on-the-fly, features very low power dissipation in the static mode and high performance in the dynamic mode. This paper shows that DML is applied in double tail comparator circuit designed in PTL design. The proposed methodology shows that delay and power achieved in DML circuit is optimized when compared to DML applied in standard CMOS design. The comparison and efficiency of proposed methodology is shown in tanner EDA v.13 tool.
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