Dual-mode power reduction technique for real-time image and video processing board

Abstract

In real-time image and video processing boards, power, speed, and area are the most often used measures for determining the performance of motion imagery applications. Due to technological advancement, power consumption has gained major attention in real-time image processing ability compared to speed. The increase in on-chip temperature due to larger power consumption has resulted in reduced operating life of chip and battery-driven devices. In this work, a new logic family has been introduced i.e., dual-mode logic (DML), which provides flexibility between the optimization of energy and delay (E-D optimization). This gate can be switched between two modes of operation that is a static mode (CMOS-like mode), which provides low power consumption and dynamic mode, which provides high speed. Recently, power leakage has become a dominant problem due to continuous data transfer among a large number of connected devices. Thus, to reduce power leakage, a self-controllable voltage level (SVL) power reduction technique is used along with DML logic. In the SVL technique, a maximum dc voltage is provided to the active load circuit on-demand or decrease the dc supplied to the load circuit in the standby mode. Integrating DML with the SVL technique reduces power consumption as well as leakage power. A 4-bit RCA, 8-bit RCA, and 16-bit RCA are used for verifying the proposed method and comparison of performance parameters is done with a conventional circuit. Complete circuit implementation and simulation are carried out in TANNER EDA version 13 tools with operating voltage of 1 V. The proposed system is further applied to real-time image, and we obtain the finest resolution level with minimum power consumption.