Performance and Analysis of 28T Full Adder using SVL Technique for Reducing Leakage Current at 45 nm Technology

Abstract

A conventional Full Adder using 28 transistors is presented here. In digital signal processors and microprocessors, the Full Adder is not only important for addition based digital circuit like multiplier and divider but is also used for accessing the address in memory. For low power requirement, there is a need to reduce leakage current in Full Adder. In this paper SVL (self controllable voltage level) technique is introduced for leakage current reduction and then standby leakage power reduction. Using SVL technique we can provide DC voltage supply as per requirement for load circuit in active mode and decrease DC voltage supply for load circuit in standby mode. This paper represents that leakage current of Full Adder using SVL technique is reduced by 61.8% as conventional Full Adder at .7volt DC supply. Simulation result is performed with 45nm CMOS technology, 20ns access time and 0.05GHZ frequency using cadence virtuoso tool.