Power Reduction in FinFET Half Adder using SVL Technique in 32nm Technology

Abstract

The greatest challenge in VLSI design is reduction of power dissipation. Due to the scaling, the leakage current of sub- threshold plays a key role in the total dissipation of power. This paper illustrates the application of reduction in power dissipation using Self-Controllable Voltage Level (SVL) Technique for a half adder using FinFETs 32nm technology. The circuit supplies a higher dc voltage to the required active-load circuit and in standby mode decreases the dc voltage given to the load circuit. Half Adder consumes low power and low leakage when compared to conservative design with SVL technique. The total power dissipation can be reduced by applying the upper Self Controllable voltage level technology that uses increased supply potential and Lower Self Controllable voltage level technology that uses raised ground potential. This paper represents how to manage power by means of SVL techniques. Based on power consumption and propagation delay the Half Adder using SVL technique is highly preferable as compared to conventional design. Low power method is anticipated to reduce power in nanoscale CMOS-VLSI systems using SVL technique. The results illustrate that there is noteworthy reduction in power incorporation of Half Adder in allusion mode. This design is greatly helpful in designing the systems that consume low power. The circuit is designed using Hspice and EDA Tools in 32nm Technology.