Design of Low Leakage Current Average Power CMOS Current Comparator Using SVL Technique

Abstract

This paper presents a low voltage, low leakage complementary metal oxide semiconductor current comparator using self-controlled voltage level technique. The self-controlled voltage level technique presents the integrated realization of an alternative method that is less intricate to implement. With the advancement in semiconductor technology, chip density and operating frequency are increasing, so the power consumption in VLSI circuit has become a major problem of consideration. This paper presented a complementary metal oxide circuit using self-controlled voltage level technique. A self-controllable voltage level (SVL) technique is mainly used to reduce leakage. In this technique when the supply voltage given 0.7V, input current given 1mA then power dissipates 165.6a#x03BC;W. By applying SVL technique on the circuit we measured the leakage power 1.233a#x03BC;W and leakage current 219.2pA then leakage current reduces 89% and leakage power reduces 35% than the traditional comparator. The technique based comparator fabricated on cadence virtuoso tool in 45nm technique. By Using this technology voltage and leakage reduces. The simulation a analytical results show that proposed circuit is correct.