Leakage Power Consumption Research Articles

Comprehensive Study of Low-Power SRAM Design Topologies

: The need for low power in portable and smart devices is the demand to be fulfilled for sustaining the semiconductor industry. Static Random Access Memory (SRAM) is the main part of the core design in chips. It is important to reduce the leakage power consumption during the steady mode of the device for the long run of the battery. This article is about the study of different modules using pre-existing low power. Application of different methods other than lowering the supply voltage leads to an increment in the number of transistors in conventional 6T (six transistor) SRAM cells like 7T to 14T. Power gating and the Multi-threshold complementary metal oxide semiconductor (MTCMOS) technique is the most relevant method. Hybrid low power techniques are in high demand because it shows better results than using individual techniques. However, the biggest challenge is to maintain the area and delay as well. FinFET came into the scenario to overcome the leakage power and short channel effect due to scaling in CMOS. Comparative study analysis shows that FinFET decreases the overall power and delay even when the number of transistors increases. A comparison was done between 6T, 8T, and 10T using FinFET and CMOS in a paper, and concluded that FinFET shows 77.792% improved write power.

AmLuCEP: Amalgamating LUT-based Compression and Adaptive Encoding Assisted Block Placement To Improve Lifetime of PCM-based Main Memories

With the rising demands for high capacity memory and poor scalability of the existing DRAM-based main memories, the emerging Non-volatile memories captures higher attention due to their high density and low leakage power consumption. However, the possible consideration of such memories as alternatives of DRAM is largely hindered by their intrinsic drawbacks like high write latency, high write energy and low write endurance. In this article, we propose an integrated solution by combining the effect of compression and encoding assisted block placement to improve lifetime of NVMs. We have developed a compression technique called LUT_Comp by exploiting the word-level redundancy present in the words of the incoming cache blocks to NVM. LUT_Comp remains effective in reducing bit-flips in NVMs by offering a balance in compression ratio and coverage (Cov). Additionally, we also propose an encoding based block placement policy that places the compressed blocks in the appropriate half within the memory. The integrated approach of compression and block placement termed AmLuCEP offers a uniform bit-flips distribution while further reducing bit-flips in NVM. Experimental results show that AmLuCEP reduces bit-flips by 54%, 42%, 37%, 21%; energy consumption by 41%, 28%, 24%, 13%; and improves lifetime by 57%, 40%, 38%, 21% over baseline and the existing techniques READ [ 38 ], COEF [ 39 ] and SELEC [ 13 ], respectively.

Ultralow-power optoelectronic synaptic transistors based on polyzwitterion dielectrics for in-sensor reservoir computing.

Bio-inspired transistor synapses use solid electrolytes to achieve low-power operation and rich synaptic behaviors via ion diffusion and trapping. While these neuromorphic devices hold great promise, they still suffer from challenges such as high leakage currents and power consumption, electrolysis risk, and irreversible conductance changes due to long-range ion migrations and permanent ion trapping. In addition, their response to light is generally limited because of "exciton-polaron quenching", which restricts their potential in in-sensor neuromorphic visions. To address these issues, we propose replacing solid electrolytes with polyzwitterions, where the cation and anion are covalently concatenated via a flexible alkyl chain, thus preventing long-range ion migrations while inducing good photoresponses to the transistors via interfacial charge trapping. Our detailed studies reveal that polyzwitterion-based transistors exhibit optoelectronic synaptic behavior with ultralow-power consumption (~250 aJ per spike) and enable high-performance in-sensor reservoir computing, achieving 95.56% accuracy in perceiving the trajectory of moving basketballs.

Performance investigation of stacked-channel junctionless Tri-Gate FinFET 8T-SRAM cell

Junctionless FinFET devices are a substitute for conventional FinFET devices due to their short channel effects and easy manufacturing at sub 22 nm technology node. The manuscript presents an 8T-SRAM cell based on tri-gate junctionless FinFET technology. The FinFET device is designed with source/drain of Si material and the channel as a stack of Si − Si 0.75 Ge 0.25 − Si. The proposed SRAM cell structure consists of a CMOS inverter with stacked p-FinFETs, improving its performance in terms of noise margin and leakage power consumption. The manuscript investigates the variation of Static Noise Margin (SNM), leakage power dissipation and delay with supply voltage to analyze the sub-threshold operation of SRAM cell. The results reveal that the cascaded p-FinFETs minimize the leakage current owing to the stack effect, resulting in improved noise margin and lower leakage power. The stacked p-FinFET devices based SRAM cell achieves 1.11x read noise margin, 1.11x hold noise margin, −1.08x write noise margin and 57.1% less leakage power compared to conventional SRAM cell at 1.0 V. However, it exhibits more delay due to increased resistance and capacitance of the cascaded transistors. The process variation analysis is also performed to investigate the SNM distribution using monte-carlo simulation by taking 10,000 samples. The results indicate that the SRAM cell structures provide higher than 6σ yield at range of supply voltages.

Notice of Violation of IEEE Publication Principles: An Energy-Efficient Heterogeneous Memory Architecture for Future Dark Silicon Embedded Chip-Multiprocessors

Main memories play an important role in overall energy consumption of embedded systems. Using conventional memory technologies in future designs in nanoscale era causes a drastic increase in leakage power consumption and temperature-related problems. Emerging non-volatile memory (NVM) technologies offer many desirable characteristics such as near-zero leakage power, high density and non-volatility. They can significantly mitigate the issue of memory leakage power in future embedded chip-multiprocessor (eCMP) systems. However, they suffer from challenges such as limited write endurance and high write energy consumption which restrict them for adoption in modern memory systems. In this article, we present a convex optimization model to design a 3D stacked hybrid memory architecture in order to minimize the future embedded systems energy consumption in the dark silicon era. This proposed approach satisfies endurance constraint in order to design a reliable memory system. Our convex model optimizes numbers and placement of eDRAM and STT-RAM memory banks on the memory layer to exploit the advantages of both technologies in future eCMPs. Energy consumption, the main challenge in the dark silicon era, is represented as a major target in this work and it is minimized by the detailed optimization model in order to design a dark silicon aware 3D Chip-Multiprocessor. Experimental results show that in comparison with the Baseline memory design, the proposed architecture improves the energy consumption and performance of the 3D CMP on average about 61.33 and 9 percent respectively.

Noninverting Schmitt trigger circuit with electronically tunable hysteresis

This paper reports a tunable hysteresis CMOS Schmitt trigger design techniques and an investigation of new buffer-based designs. The sizing of the two feedback inverters controls the two trip points of the structure independently. By the addition of voltage tune controlled sourcing transistor, the hysteresis window can be easily changed. Moreover, the new designs are immune to the kick-back noise coming from the succeeding inverter blocks. In this work, the VT-ST proves itself more reliable regarding dynamic and leakage power consumption and propagation delay. In this work, aspect ratio of the transistors is kept as small as possible, and the hysteresis loop is varied with a tunable voltage transistor. 5000 Monte Carlo simulations reveal that the VT-ST is more reliable as ΔVLHandΔVHL are almost equal, and a small variation is observed. For the comprehensive analysis, a figure of merit for all the circuits is derived and it is 3.16× higher for the proposed VT-ST than the conventional circuit. All simulation work is handled by the cadence virtuoso tool using UMC 40 nm technology.

Embedding security into ferroelectric FET array via in situ memory operation

Non-volatile memories (NVMs) have the potential to reshape next-generation memory systems because of their promising properties of near-zero leakage power consumption, high density and non-volatility. However, NVMs also face critical security threats that exploit the non-volatile property. Compared to volatile memory, the capability of retaining data even after power down makes NVM more vulnerable. Existing solutions to address the security issues of NVMs are mainly based on Advanced Encryption Standard (AES), which incurs significant performance and power overhead. In this paper, we propose a lightweight memory encryption/decryption scheme by exploiting in-situ memory operations with negligible overhead. To validate the feasibility of the encryption/decryption scheme, device-level and array-level experiments are performed using ferroelectric field effect transistor (FeFET) as an example NVM without loss of generality. Besides, a comprehensive evaluation is performed on a 128 × 128 FeFET AND-type memory array in terms of area, latency, power and throughput. Compared with the AES-based scheme, our scheme shows ~22.6×/~14.1× increase in encryption/decryption throughput with negligible power penalty. Furthermore, we evaluate the performance of our scheme over the AES-based scheme when deploying different neural network workloads. Our scheme yields significant latency reduction by 90% on average for encryption and decryption processes.

Design of Enhanced Reversible 9T SRAM Design for the Reduction in Sub-threshold Leakage Current with14nm FinFET Technology

Power dissipation is considered one of the important issues in low power Very-large-scale integration (VLSI) circuit design and is related to the threshold voltage. Generally, the sub-threshold leakage current and the leakage power dissipation are increased by reducing the threshold voltage. The overall performance of the circuit completely depends on this leakage power dissipation because this leakage and power consumption causes the components that are functioning by the battery for a long period to be washed-out rapidly. In this research, the reversible logic gate-based 9T static random access memory (SRAM) is designed in 14nm FinFET technology to reduce leakage power consumption in memory related applications. The Schmitt-trigger (ST)-based 9T SRAM cell is designed to attain high read-write stability and low power consumption using a single bit line structure. The reversible logic gates of Feynman (FG) and Fredkin gate (FRG) are combined to develop a row and column decoder in an SRAM design to diminish the leakage power. Moreover, the transistor stacking effect is applied to the proposed memory design to reduce the leakage power in active mode. The proposed reversible logic and transistor stacking based SRAM design is implemented in Tanner EDA Tool version 16.0. It also performs both read and write operations using the proposed circuit. The performance measures of read access time (RAT), write access time (WAT), read, write, and static power by varying supply voltage and temperature, delay and stability analysis (read/write static noise margin) are examined and compared with existing SRAM designs.

Energy-Efficient Joint Scheduling of Pumps and Valves in Water Distribution Network Using Hybrid Optimization Algorithm

Traditionally, pumping efficiency and pressure control have been studied as separate disciplines in water companies, with a focus on optimizing pump operation and managing leakage. Present-day siphons are frequently outfitted with variable speed drives; consequently, the siphon outlet tension could be constrained by controlling siphon speed. If there are siphons upstream from a tension-decreasing valve (PRV) with no moderate tank, the PRV gulf strain could be diminished by changing siphoning in the upstream piece of the organization. In addition, when optimizing pump operation, consideration should be given to the impact of pressure-dependent leakage on the resulting schedules. Thus, this article considers the streamlining of siphon and valve plans for complex huge-scope water circulation organizations (WDN). The review takes care of the siphoning booking issue, which tries to acquire the timetable of on/off switches for each siphon and valve that limits energy power cost, taking into account the energy consumed by the functioning siphons. This schedule generates the flow and pressure through the network and it has to satisfy the demand for all nodes, conserve energy, to minimize head loss. To execute and safeguard clean water assets, functional improvement of WDSs should consider both energy and upkeep costs while deciding the ideal timetable for siphons and valves. The point of this examination is to create and confirm an energy model that can work on the effectiveness of equal siphon frameworks. Accordingly, the research proposed the mathematical model of shaft power consumption using the quadratic polynomial fitting. Additionally, investigated the potential application of Variable Speed Pumps (VSPs) to improve pressure reliability, leakage, and electrical power consumption in Water Distribution Networks (WDNs). To execute and safeguard clean water assets, functional improvement of Water Circulation Frameworks (WDSs) should consider both energy and upkeep costs while deciding the ideal timetable for siphons and valves. The point of this examination is to create and confirm an energy model that can work on the effectiveness of equal siphon frameworks. The hybrid binary dragonfly-enhanced Particle Swarm Optimization (PSO) algorithm is proposed for joint pumping and valve scheduling problems in WDS. The optimal scheduling is conducted based on three different energy tariffs. The Matlab programming climate is utilized to demonstrate this strategy with the assistance of the EPANet Matlab tool compartment. Analyzing a range of scenarios with varying time frames, operational limitations, and network changes, the proposed WDN solution showed its capability to efficiently create and address optimization challenges tailored to diverse needs.

Enhanced Quasi-Static Energy Recovery and Modified Clock Gating for the Wallace Tree Multiplier with Reversible Adders

High-speed, low-power digital circuits are essential in many digital applications. The objective of the paper is to design high-speed low-power multipliers with reversible gates. The realization of a multiplier with an efficient clocking system is also presented to reduce leakage power consumption. The existing reversible configurations do not possess an effective clocking system for reducing power in an idle state. In this work, a modified clock gating (MCG) and Enhanced Quasi-Static Energy Recovery Logic (EQSERL) are designed to generate a clock pulse. The EQSERL reduces the dynamic state in the circuit and it is designed with reduced complexity. This process effectively reduces leakage power consumption in the circuit. The conventional clock gating circuit is modified for connecting it with the EQSERL. This MCG circuit reduces unwanted power consumption. The conventional Wallace tree multiplier (WTM) involves full adder and half adder circuits. In this proposed work, a square root carry select adder (SQRT CSLA) with a reversible binary to excess-1 converter (BEC) and a ripple carry adder is presented. The reversible gates such as the Feynman gate, the Toffoli gate, and the dual key gate are employed. Finally, the proposed architecture is tested with different clocking circuits using Synopsys tools and the performance metrics like delay and power are observed.

Design and Analysis of Static Random-Access Memory FinFET Circuit Using Self Controlled Voltage Level Controller

Researchers in the field of device research are always searching for a device that meets certain criteria, such as having low leakage and a low threshold voltage, without sacrificing performance. This pursuit has led to the development of numerous gate architectures. As a result of the enormous size of the static random-access memory (SRAM), its yield and leakage power consumption account for the majority of the chip’s total yield and leakage power consumption respectively. However, as CMOS technology continues to grow in the sub-65 nanometer domain to lower the cost of transistors and the dynamic power, it presents a number of issues on the design of SRAM. In this paper, a 6T SRAM cell with differential write and single ended read operations working in the near-threshold region is proposed. The structure is based on modifying a recently proposed 6T cell which uses high and low VTH transistors to improve the read and write stability. Also, the changes of cell parameters when the temperature rises from 40 °C to 100 °C are investigated. Finally, the write margin as well as the read and hold SNMs of the cell are studied at two supply voltages of 400 mV and 500 mV.

Contact-engineered reconfigurable two-dimensional Schottky junction field-effect transistor with low leakage currents

Two-dimensional (2D) materials have been considered promising candidates for future low power-dissipation and reconfigurable integrated circuit applications. However, 2D transistors with intrinsic ambipolar transport polarity are usually affected by large off-state leakage currents and small on/off ratios. Here, we report the realization of a reconfigurable Schottky junction field-effect transistor (SJFET) in an asymmetric van der Waals contact geometry, showing a balanced and switchable n- and p-unipolarity with the Ids on/off ratio kept >106. Meanwhile, the static leakage power consumption was suppressed to 10−5 nW. The SJFET worked as a reversible Schottky rectifier with an ideality factor of ~1.0 and a tuned rectifying ratio from 3 × 106 to 2.5 × 10−6. This empowered the SJFET with a reconfigurable photovoltaic performance in which the sign of the open-circuit voltage and photo-responsivity were substantially switched. This polarity-reversible SJFET paves an alternative way to develop reconfigurable 2D devices for low-power-consumption photovoltaic logic circuits.

Novel PVT Resilient Low-Power Dynamic XOR/XNOR Design Using Variable Threshold MOS for IoT Applications

A variable threshold voltage hybrid evaluation network based dynamic XOR/XNOR gate is presented to reduce the parameters leakage power dissipation, dynamic power, and layout area compared to existing dynamic gates under similar delay time conditions. This study explores the impacts of process, supply voltage, and temperature changes on leakage power dissipation and dynamic power using Monte Carlo simulation. The Monte Carlo analysis demonstrates that leakage power dissipation and dynamic power reduction have significantly improved. Furthermore, when compared to hybrid type dynamic XOR/XNOR (N-type XOR/XNOR), the proposed design reduces leakage power and dynamic power consumption by 6.1% (54.0%) and 18.75% (35.0%), respectively. While the proposed design has a slight layout area penalty compared to a hybrid type dynamic XOR/XNOR, it offers the same amount of the layout area as a traditional N-type XOR/XNOR.

MRAM-Based Cache System Design and Policy Optimization for RISC-V Multi-Core CPUs

On-chip cache, being the crucial constituent of central processing unit (CPU), accounts for a pivotal portion of the system’s overall power consumption. The typical SRAM-based cache is vulnerable to high static leakage power consumption, while multiple challenges encountered in scaling up its capacity. In the paper, magnetic random-access-memory (MRAM) cache is considered as a promising candidate in RISC-V CPU systems. After analyzing the performances of single-core, dual-core, quad-core, and octa-core systems, a quad-core RISC-V based CPU system with a two- level hierarchical cache structure is designed, in which Spin-Orbit Transfer (SOT)-MRAM is adopted as the L1 private cache and Spin-Transfer Torque (STT)-MRAM as the L2 shared cache. Details on the microarchitecture of the multi-core CPU design are provided. Energy evaluation shows that this quad-core cache system can achieve 66.4% leakage power saving and 34.5% total power saving compared to SRAM. For high efficiency of data-exchange in the novel MRAM CPU systems, three types of characteristics optimizing methods are proposed. An optimized cache-coherency protocol incorporating non-inclusive policy is proposed. The quad-core system is updated by adding the coherence control module and a directory in the design scheme. The simulation results on multiple dimensions show that the policy of the hybrid MRAM memory is a promising candidate for multi-core RISC-V system, with the benefits of low-power consumption and high hit rate. Finally, the peripheral circuitry and manufacturing cost for the implementation of the MRAM cache is discussed in the paper.

Self-Assembled Monolayer for Low-Power-Consumption, Long-Term-Stability, and High-Efficiency Quantum Dot Light-Emitting Diodes

Quantum dot light-emitting diodes (QLEDs) are an emerging class of optoelectronic devices with a wide range of applications. However, there still exist several drawbacks preventing their applications, including long-term stability, electron leakage, and large power consumption. To circumvent the difficulties, QLEDs based on a self-assembled hole transport layer (HTL) with reduced device complexity are proposed and demonstrated. The self-assembled HTL is prepared from poly[3-(6-carboxyhexyl)thiophene-2,5-diyl] (P3HT-COOH) solution in N,N-dimethylformamide (DMF) forming a well-ordered monolayer on an indium-tin-oxide (ITO) anode. The P3HT-COOH monolayer has a smaller HOMO band offset and a sufficiently large electron barrier with respect to the CdSe/ZnS quantum dot (QD) emission layer, and thus it is beneficial for hole injection into and electron leakage blocking from the QD layer. Interestingly, the QLEDs exhibit an excellent conversion efficiency (97%) in turning the injected electron-hole pairs into light emission. The performance of the resulting QLEDs possesses a low turn-on voltage of +1.2 V and a maximum external quantum efficiency of 25.19%, enabling low power consumption with high efficiency. Additionally, those QLEDs also exhibit excellent long-term stability without encapsulation with over 90% luminous intensity after 200 days and superior durability with over 70% luminous intensity after 2 h operation under the luminance of 1000 cd m-2. The outstanding device features of our proposed QLEDs, including low turn-on voltage, high efficiency, and long-term stability, can advance the development of QLEDs toward facile large-area mass production and cost-effectiveness.

Performance Analysis of the C/C Composite Cylindrical Reverse Inter-Shaft Gas Film Seal

The reverse inter-shaft gas film seal is a gas path seal used in the intermediate bearing cavity of an aero-engine, which is challenging to implement due to its special installation and usage conditions. This paper proposes a C/C (Carbon/Carbon) composite cylindrical reverse inter-shaft seal structure and carries out a performance simulation analysis based on bidirectional fluid–solid coupling technology. The results show that the cylindrical reverse inter-shaft gas film seal with double-layer C/C composite sealing rings with different material mesoscopic parameters can balance seal leakage and friction power consumption and is beneficial to improving the comprehensive performance of the seal. As the mesoscopic parameters of the inner sealing ring material increase in warp and weft density, the sealing leakage rate decreases, and the gas film force and gas friction power consumption all increase. As the pressure difference increases, the sealing leakage rate and gas film force increase. As the rotation speed of the inner and outer rotors increases, the seal leakage rate increases, and the gas film force decreases. A C/C composite sealing ring cylindrical reverse inter-shaft gas film seal has a lower leakage rate and larger gas film force than a graphite sealing ring cylindrical reverse inter-shaft seal, which confers certain performance advantages. The work in this paper can provide a reference for the design of reverse inter-shaft seals.

Schmitt Trigger 12T1M Non-volatile SRAM cell with improved process variation tolerance

This paper presents a Schmitt Trigger (ST) based 12T1M non-volatile static random-access memory (nvSRAM) cell which significantly provides tolerance against process variations. The memristor M1 is connected between internal node Q and bitline RBL through read pass transistor. The impact of process variation is studied on margin and delay performances of proposed and existing read decoupled (RD) nvSRAM cells. The proposed cell achieves 1.62X, 1.17X and 1.33X higher write, read and hold margins, respectively, in comparison to existing RD nvSRAM cells. Furthermore, the maximum reduction in write, read and hold failure probabilities by 105×, 104× and 104×, respectively, is observed for proposed cell. The overall Vmin of proposed cell is found as 425 mV which is minimum among the existing RD counterparts. In addition, there is significant reduction in leakage power consumption and write/read delay deviation for the proposed cell. The store/restore performance of the proposed cell is same as most of the considered cells. All the comparison are made using 32 nm CMOS PTM model and at Vdd = 0.6 V. The effect of supply voltage variation is also studied on the performance of proposed and existing RD nvSRAM cells for the sake of completeness.

Low-Power 6T SRAM Cell using 22nm CMOS Technology

Static Random-Access Memory (SRAM) occupies approximately 90% of total area on a chip due to high number of transistors used for a single SRAM cell. Therefore, SRAM cell becomes a power-hungry block on a chip and it becomes more prominent at lower technologies from both dynamic and static perspective. Static power consumption is due to leakage current associated with the transistors that are off and dynamic power consumption is due to charging and discharging of the circuit capacitance. As gate length or channel length decreases gate oxide thickness also scales down. Scaling down of conventional transistor results in huge tunneling of electron from gate into channel leading to higher leakage power consumption. So, transistor with metal gate, high-k dielectric and strained-Si is used which shows better result in terms of low-power consumption, better performance with acceptable delay. Among various topologies of SRAM cell 6T is considered as a suitable choice for low power applications.

Experimental test and theoretical modeling on the working characteristics of spherical water pump

This paper investigates working characteristics of a spherical water pump through the experimental test and theoretical modeling. Both theoretical models of displacement and the real time delivered flow are established precisely based on the working principles of spherical pump, under spherical and polar coordinate systems, to investigate the effects structural parameters on flow characteristics. A test rig is established to investigate and validate the working characteristics of spherical pump. Performance such as leakage characteristics, flow characteristics, power consumption and noise radiation are tested, and the theoretical models are validated under multiple working conditions. Results indicate the proposed models are effective to characterize the working properties of spherical water pump, which also demonstrates reasonable performance on the power consumption and noise radiation characteristics. These studies provide fundamental principles for abiding in designing the high-performance spherical water pump.

A comprehensive analysis of different 7T SRAM topologies to design a 1R1 W bit interleaving enabled and half select free cell for 32 nm technology node

In this paper, a single-ended, dual port, 1R1 W seven transistor-based static random access memory bit cell is presented. The cell is designed based on a detailed review of various pre-existing 7T cells. All the cells in the paper are evaluated at 32 nm technology and supply voltage of 0.8 V. The static analysis reveals that the hold/read noise margins for the proposed cell are 324 mV each, whereas the write margin is 488 mV. Successful read and write operation for the cell requires a pulse-width of 5 ps and 0.14 ns, respectively. The temperature variation and process corner analysis are used to justify the reliability for the proposed cell. The former analysis yields 0.15 and 0.24 mV/°C variation in the HSNM/RSNM, and WM for the cell. The current ratio for the cell is comparatively higher than other cells. The leakage power consumption for the cell is 256 pW, while its read and write power consumption are 6 µW and 1.9 µW, respectively. Also, the cell is half select disturbance-free and therefore supports bit-interleaving. This ensures the increased reliability for the cell. All the aforementioned merits for the cells are achieved with a minimal layout area of 0.553 µm2.