MRAM-Based Cache System Design and Policy Optimization for RISC-V Multi-Core CPUs

Abstract

On-chip cache, being the crucial constituent of central processing unit (CPU), accounts for a pivotal portion of the system’s overall power consumption. The typical SRAM-based cache is vulnerable to high static leakage power consumption, while multiple challenges encountered in scaling up its capacity. In the paper, magnetic random-access-memory (MRAM) cache is considered as a promising candidate in RISC-V CPU systems. After analyzing the performances of single-core, dual-core, quad-core, and octa-core systems, a quad-core RISC-V based CPU system with a two- level hierarchical cache structure is designed, in which Spin-Orbit Transfer (SOT)-MRAM is adopted as the L1 private cache and Spin-Transfer Torque (STT)-MRAM as the L2 shared cache. Details on the microarchitecture of the multi-core CPU design are provided. Energy evaluation shows that this quad-core cache system can achieve 66.4% leakage power saving and 34.5% total power saving compared to SRAM. For high efficiency of data-exchange in the novel MRAM CPU systems, three types of characteristics optimizing methods are proposed. An optimized cache-coherency protocol incorporating non-inclusive policy is proposed. The quad-core system is updated by adding the coherence control module and a directory in the design scheme. The simulation results on multiple dimensions show that the policy of the hybrid MRAM memory is a promising candidate for multi-core RISC-V system, with the benefits of low-power consumption and high hit rate. Finally, the peripheral circuitry and manufacturing cost for the implementation of the MRAM cache is discussed in the paper.