Laterally Diffused Metal Oxide Semiconductor Research Articles

Total-Ionizing-Dose Radiation-Induced Dual-Channel Leakage Current at Unclosed Edge Termination for High Voltage SOI LDMOS

Total-ionizing-dose (TID) radiation response on unclosed edge termination is investigated for high voltage silicon-on-insulator (SOI) laterally diffused metal-oxide-semiconductor (LDMOS) in this article. Radiation-induced dual-channel leakage current model is proposed to reveal the mechanism of leakage current generation at OFF-state. Radiation causes a mass of positive oxide trapped charges generated in field oxide (FOX) layer and buried oxide layer. Owing to the P-SOI layer with significantly low doping concentration, two inversion channels are formed at the surface and bottom in the edge termination region, which provides parallel conduction paths. Electrons from the source N+ are pulled down and flow along the bottom channel while punchthrough occurring. The radiation-induced leakage current could be suppressed by thinning FOX layer, increasing the doping concentration of the P-SOI layer, and thickening the SOI layer.

A Ultra-Low Specific On-Resistance and Extended Gate SJ LDMOS Structure

A new structure of extended gate (EG) SJ LDMOS is proposed in this paper to overcome the substrate assisted depletion (SAD) effect in the structure of Super-Junction lateral double diffused metal oxide semiconductor (SJ LDMOS). Different from other surface SJ structures, the SJ layer of the structure is located in the body of the drift region. Gate oxide and silicon layer form the EG Structure-Oxide-Semiconductor structure that is similar to Metal–Insulator–Semiconductor capacitor. The the N-drift of the EG structure can obtain the charge compensation to overcome the SAD effect, and a nearly rectangular electric field is achieved. In the on-state, the EG structure has two conductive channels and the accumulation layer is formed on the drift region. By accumulating high concentration electrons in the channels, the specific on-resistance (RON,sp) is greatly reduced. When the drift length is 24 μm, 431.4 V breakdown voltage (VB) and 9.8 mΩ cm2 RON,sp are achieved, and the figure of merit is 18.9 MW cm−2.

IFMIF-DONES RF System

The IFMIF-DONES accelerator cavities require around 5.7 MW of continuous RF power at 175 MHz to deliver a 125 mA and 40 MeV deuteron beam at the lithium target. The IFMIF-DONES RF System is composed of 56 RF Stations able to provide up to 200 kW RF power at 175 MHz in CW, delivering a grand total of 7.4 MW.Such a massive system requires an ambitious approach to be able to comply with the accelerator requirements with a high efficiency and a high availability. The newest advancements in the field of RF systems for accelerators, which are already implemented independently in some facilities, are integrated for the first time in a single system from the early design phases. The result of this approach is the RF Station, which is a totally independent and compact RF module containing all the components needed to feed, control, and protect the accelerator cavities. The amplification technology chosen is the Laterally-Diffused Metal-Oxide Semiconductor (LDMOS) transistor, providing a good efficiency and high robustness. The proposed RF power combination of up to 160 transistors is based on resonant cavity combiner, allowing a single-step combination that highly reduces the losses with respect to more traditional corporate combining schemes. In this proposal, the RF generation relies on a fully digital Low-Level RF (LLRF) providing accurate amplitude/phase control and high flexibility to implement all the required functions for a proper cavity operation. The RF Station has been designed maximizing the modularity and the reliability. In order to achieve the required modularity, the LDMOS transistors have been grouped in Amplifier Modules (AMDs) containing four of them but keeping independent outputs. Furthermore, the AC/DC power converters have also been grouped in modules feeding a common DC bus. The RF Station will have redundant modules to be able to operate properly in any condition, even with some of them failed.This innovative proposal for the IFMIF-DONES RF System design and detailed information on the RF Stations architecture are presented in this paper.

Fully integrated three-way LDMOS Doherty PAs for 1.8–2.2 GHz dual-band and 2.6 GHz m-MIMO 5G applications

AbstractThis paper presents a fully integrated three-way Doherty architecture to address the challenges of 5G applications using laterally-diffused metal-oxide semiconductor (LDMOS) technology. By using the so-called CDS cancelation method for the Doherty combiner design, a wideband impedance transformation is achieved, that combined with the three-way Doherty power amplifier (DPA) architecture allows for high efficiency in deep back-off, with a reduced load modulation for high bandwidth. Throughout this paper, the design approach and realization are described, while multiple critical design challenges will be addressed such as low frequency drain resonance optimization, impact of in-package coupling effects, and linearity versus efficiency tradeoff. Two state-of-the-art three-way fully integrated LDMOS DPA monolithic microwave integrated circuit (MMICs) are presented to demonstrate how these measures have been successfully applied to different power amplifier (PA) line-up components for 5G base station systems. First, a 60 W 1.8–2.2 GHz multi-stage device for driver application in true dual-band operation is presented. The circuit design pays special attention to extended PA video bandwidth thanks to integrated passive device. After digital pre-distortion (DPD) in dual-band operation, this highly linear device achieves an outstanding adjacent channel leakage ratio (ACLR) of −56 dBc for a 2cLTE 20 MHz 8 dB peak-to-average ratio signal spaced by 345 MHz, thus 385 MHz instantaneous bandwidth (IBW), with 29% efficiency at 35 dBm, 12 dB output back-off (OBO). Second, the simulation and measurement results of a 55 W 2.6 GHz multi-stage DPA for massive-MIMO final stage application are presented, which yields an excellent linearized efficiency of 49% using a 200 MHz 10cLTE signal with an ACLR lower than −47.5 dBc. For 8cLTE 20 MHz (160 MHz IBW), the device yields 50% efficiency with −50.7 dBc ACLR linearized after DPD. The achieved efficiency is well comparable to published GaN DPAs. These results were achieved by improved simulation techniques to minimize frequency dispersion and thus allow high efficiency operation over wide bandwidth. Both devices show that LDMOS is not only a mature technology which allows those PAs to be reliable and low-cost for mass production in very compact packages, but also provide best-in-class RF performance according to the needs of 5G base station systems.

Improved Model on Buried-Oxide Damage Induced by Total-Ionizing-Dose Effect for HV SOI LDMOS

In this article, an improved model on buried-oxide (BOX) damage induced by total-ionizing-dose (TID) effect considering positive oxide trapped charge ( N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ot</sub> ) generated in silicon on insulator (SOI)/BOX interface under negative electric field bias (field lines perpendicular to the SOI/BOX interface pointing from the top to the bottom of the BOX) and N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ot</sub> saturation effect is proposed and adopted in accurate simulated analysis to predict the postirradiation device behavior. Moreover, the mechanism of high-voltage (HV) SOI lateral double diffused metal oxide semiconductor field effect transistor (LDMOS) degradation during irradiation is also revealed by the proposed accurate simulation method. Tolerance design for radiation-hardened HV SOI LDMOS is discussed with the aid of the presented model. The tradeoff between postirradiation electrical characteristics and fresh electrical characteristics should be taken into account to meet the radiation hardening requirement. The radiation-hardened-by-design LDMOS introduced in this article keeps an OFF-state breakdown voltage above 120 V at D = 500 krad(Si) with operating voltage equal to 80 V, which is fabricated on a commercial SOI substrate material with plain interface quality parameters. The corresponding hardening strategy is also given.

Simulation Study on the Optimization and Scaling Behavior of LDMOS Transistors for Low-Voltage Power Applications

We present a systematic investigation of device optimization for laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistors in terms of subthreshold leakage current, breakdown voltage, and ON-resistance for low-voltage ( $10\boldsymbol {^{-13}}\text{A}/\boldsymbol {\mu }\text{m}$ while maintaining a breakdown voltage exceeding 10 V for channel lengths down to 10 nm. Interestingly, we find an optimal ON-resistance for a channel length of 40 nm, while for shorter channel lengths the ON-state resistance increases with decreasing channel length. The increasing resistance for shorter channels is caused by electron mobility degradation as a result of an increasing body doping, needed to limit the leakage current. The optimal channel length presents a limit to conventional scaling of LDMOS devices, commonly used in low-voltage power applications.

전산모사 시뮬레이션을 이용한 Laterally Diffused MOS(LDMOS)에서의 Displacement Defect의 영향

The effect of displacement defect due to radiation effect is investigated in laterally diffused metal oxide semiconductor (LDMOS) using technology computer-aided design (TCAD) simulation. The displacement defect with acceptor-like trap of deep level (Ec-0.4eV) under shallow trench isolation (STI) induces the worst degradation of Id-Vg characteristic. The location of defect under STI with lightly doping concentration is the worst position to transfer characteristic of Id-Vg. For breakdown voltage characteristic, the positions and types of displacement trap are negligible, because of high drain voltage operation.

Improvement of electrostatic discharge current-handling capability for high-voltage multi-finger nLDMOS devices with self-triggered technique

The structure of the conventional laterally diffused metal-oxide semiconductor (LDMOS) is modified to be fit for application of a self-triggered technique in multi-fingered high-voltage LDMOS devices to enhance the electrostatic discharge (ESD) current-handling capability. Device simulation and transmission line pulse testing are employed to analyze the working mechanism and ESD performance of the proposed device with self-triggered technique based on a 0.5 µm 24 V CMOS DMOS (CDMOS) process. According to the measurement results, compared to traditional gate-grounded LDMOS, the secondary breakdown current () of the proposed device with low-trigger-voltage triggering finger can be drastically improved from 2.43 A to 5.57 A, and its trigger voltage () is reduced from 59.91 V to 48.18 V.

Layout Strengthening the ESD Performance for High-Voltage N-Channel Lateral Diffused MOSFETs

An electrostatic discharge (ESD) event can negatively affect the reliability of integrated circuits. Therefore, improving on ESD immunity in high-voltage (HV) n-channel (n) lateral diffused metal–oxide–semiconductor field-effect transistor (HV nLDMOS) components through drain-side layout engineering was studied. This involved adjusting the operating voltage, improving the non-uniform turned-on phenomenon, and examining the effects of embedded-device structures on ESD. All proposed architectures for improving ESD immunity in this work were measured and evaluated using a transmission-line pulse system. The corresponding trigger voltage (Vt1), holding voltage (Vh) and secondary breakdown current (It2) results of the tested devices were obtained. This paper first addresses the drift-region length modulation to design different operating voltages, which decreased as the drift region length and shallow trench isolation (STI) length shrunk. When an HV nLDMOS device decreased to the shortest drift region length, the Vt1 and Vh values were closest to 21.85, and 9.27 V, respectively. The It2 value of a low-voltage operated device could be increased to a maximum value of 3.25 A. For the channel width modulation, increasing the layout finger number of an HV LDMOS device did not really help the ESD immunity that because it may suffer the problem of non-uniform turned-on phenomenon. Therefore, adjusting the optimized channel width was the best one method of improvement. Furthermore, to improve the low ESD reliability problem of nLDMOS devices, two structures were used to improve the ESD capability. The first was a drain side—embedded silicon-controlled rectifier (SCR). Here, the SCR PNP-arranged type in the drain side had the best ESD capability because the SCR path was short and had been prior to triggering; however, it also has a latch-up risk and low Vh characteristic. By removing the entire heavily doped drain-side N+ region, the equivalent series resistance in the drain region was increased, so that the It2 performance could be increased from 2.29 A to 3.98 A in the structure of a fully embedded drain-side Schottky diode. This component still has sufficiently high Vh behaviour. Therefore, embedding a full Schottky-diode into an HV nLDMOS in the drain side was the best method and was efficient for improving the ESD/Latch-up abilities of the device. The figure of merit (FOM) of ESD, Latch-up, and cell area considerations improved to approximately 80.86%.

Temperature impact on reliability of power RF devices under S-band pulsed-RF test

This paper presents an innovative reliability bench of aging life tests designed to high power applications for device lifetime under pulse conditions. The temperature effect on the parameters of power LDMOS (Radio Frequency Laterally Diffused-Metal–Oxide–Semiconductor) devices is highlighted. Indeed, the acceleration of the degradation mechanisms is related, directly or indirectly, to the temperature variation. The tests carried out on the power amplifier will be Life-test RF type (accelerated aging under constant constraints) over a period of 1500 h to quantify the drifts of the parameters measured (mainly POUT and IDSS) under reliability bench life-test at different temperatures. The parameters of devices have been characterized i.e. static, dynamic and before and after testing. This allows us to quantify the degradation, of the shift, of a certain number of electrical quantities (VTH, GM, RDSON, CRSS, etc.). The analysis of the physical results has been presented (simulator 2D ATLAS-SILVACO) to explain and observe the physical review of temperature impacts on power LDMOS performance. Finally, initial impacts analysis have been discussed.

Variable-K double trenches SOI LDMOS with high-concentration P-pillar**Project supported by the Scientific Research Fund of Hunan Provincial Education Department, China (Grant No. 19K001).

A variable-K trenches silicon-on-insulator (SOI) lateral diffused metal–oxide–semiconductor field-effect transistor (MOSFET) with a double conductive channel is proposed based on the enhancement of low dielectric constant media to electric fields. The device features variable-K dielectric double trenches and a P-pillar between the trenches (VK DT-P LDMOS). The low-K dielectric layer on the surface increases electric field of it. Adding a variable-K material introduces a new electric field peak to the drift region, so as to optimize electric field inside the device. Introduction of the high-concentration vertical P-pillar between the two trenches effectively increases doping concentration of the drift region and maintains charge balance inside it. Thereby, breakdown voltage (BV) of the device is increased. The double conductive channels provide two current paths that significantly reduce specific on-resistance (Ron,sp). Simulation results demonstrate that a 17-μm-length device can achieve a BV of 554 V and a low on-resistance of 13.12 mΩ⋅cm2. The Ron,sp of VK DT-P LDMOS is reduced by 78.9% compared with the conventional structure.

The New Structure and Analytical Model of a High-Voltage Interconnection Shielding Structure With High-k Dielectric Pillar

The high-voltage interconnection (HVI) effect induces electric field crowding near the source region of power lateral double diffused metal oxide semiconductor field effect transistors (LDMOSs) and, therefore, weakens its breakdown voltage (BV) characteristic. To suppress such a detrimental effect, a novel HVI structure with a high- ${k}$ dielectric pillar beneath the HVI metal line is proposed. An analytical model is proposed to reveal the mechanism of the proposed structure and explain the effects of the parameters of the structure. The analytical model indicates that the high- ${k}$ dielectric pillar eliminates the electric field crowding near the source, promotes the depletion of the drift region, and avoids the premature breakdown. Meanwhile, due to the existence of the high- ${k}$ dielectric pillar, the surface electric field profile in the drift region can be modulated, and the influence of HVI can be effectively suppressed. Thus, a higher BV is obtained. The simulation results indicate that the proposed structure presents better BV, which is the same as that of the reduced surface field (RESURF) structure without HVI.

Snapback‐free RC‐LIGBT with integrated LDMOS and LIGBT

A novel reverse-conducting lateral insulated-gate bipolar transistor (RC-LIGBT) merged with an independent LDMOS region and LIGBT region is proposed, which is named M-RC-LIGBT. The forward conduction of the M-RC-LIGBT is divided into three steps, firstly it works in laterally-diffused-metal-oxide semiconductor (LDMOS) mode with single electron, and then it works in LDMOS and LIGBT modes with electron and hole, and finally it is dominated by the LIGBT mode. There is no abrupt current observed in the forward conduction, thus the snapback phenomenon is eliminated. At the reverse conduction, the M-RC-LIGBT integrates an inner diode, and the P-body acts as the anode and the N-collector acts as the cathode of the diode, respectively, thus the reverse conduction ability is achieved. As the results show, the M-RC-LIGBT has superior forward and reverse conduction properties, the V F and V R are 0.94 and 0.82 V, respectively, which are decreased by 61 and 18% when compared to the conventional RC-LIGBT, respectively.

Channel Length Optimization for Planar LDMOS Field-Effect Transistors for Low-Voltage Power Applications

We identify an optimum channel length for planar Laterally Diffused Metal-Oxide-Semiconductor (LDMOS) field-effect transistors, in terms of the specific on-resistance, through systematic device simulation and optimization. We simulate LDMOS devices with different channel lengths ranging from 100 nm to 10 nm, modifying the length of the drift region and doping concentration of the body region to match a pre-determined leakage current suitable for low-voltage power applications (3.3V and 5V). For devices with a channel length exceeding 40 nm, reducing the channel length decreases the on-resistance as expected. Below 40 nm, an increase in resistance is observed as the result of an increased body doping concentration leading to significant electron mobility degradation in the channel area.

Optimization and Experiments of Lateral Semi-Superjunction Device Based on Normalized Current-Carrying Capability

A lateral double diffused metal oxide semiconductor transistor with the semi-superjunction (semi-SJ LDMOS) is optimized based on the normalized current-carrying capability (CC) and experimentally realized in this letter. The device is fabricated based on an optimized equivalent substrate and the semi-SJ is introduced near the source. The semi-SJ increases the local doping concentration in the N regions meanwhile reduces the current path area and carrier mobility, resulting in the variation of CCs before and after the introduction of the semi-SJ. The normalized CC factor $\eta _{\text {C}}$ is proposed to evaluate this variation, with which the minimum specific on-resistance ${R} _ {\text {ON}, \text {sp}}$ is predicted by the condition of $\eta _{\text {C}}= {1}$ . The experiments of the semi-SJ LDMOS exhibit a minimum ${R} _ {\text {ON}, \text {sp}}$ of 25.5 $\text{m}\Omega \cdot $ cm2 under a breakdown voltage ${V} _{{\text {B}}}$ of 464.3 V. This represents a reduction in ${R} _ {\text {ON}, \text {sp}}$ by 37.7% when compared with the theoretical ${R} _ {\text {ON}, \text {sp}}$ of triple RESURF devices.

Physics-Based Capacitance Model of Drift Region in Laterally Diffused Metal-Oxide Semiconductor and Its Implementation with BSIM4.

A physical capacitance model is presented for the drift region in a laterally diffused metal-oxide semiconductor (LDMOS). It is derived as a surface-potential-based model of nodal charge for the drift region. The model is combined with BSIM4, which is for the intrinsic MOSFET region of LDMOS, and it is validated with TCAD and measurement data. The model accurately predicts the capacitance of each node for the entire bias region.

A Novel High Voltage Ultra-Thin SOI-LDMOS With Sectional Linearly Doped Drift Region

A novel high voltage ultra-thin silicon on insulator (SOI) lateral double diffused metal oxide semiconductor field effect transistor (LDMOS) with a sectional linearly doped drift region is proposed and experimentally realized in this letter. The new device features a sectional linear doping (SLD) in a 0.17 μm SOI layer with a source field plate covering the full drift region. Low specific on-resistance Ron,sp is obtained by increasing the local doping concentration of the high resistance region. An analytical model is developed to provide the design guidance for the thin SOI devices with the field plate. The experimental results of the SOI SLD-LDMOS demonstrate that the new device shows a high breakdown voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> of 960 V with a superior figure of merit (FOM = V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> / R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> ) of 5.98 MW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> when comparing with other reported thin SOI devices. Good agreements are observed between the model and the experimental results.

A 600-V Super-Junction pLDMOS Utilizing Electron Current to Enhance Current Capability

In this paper, a super-junction p-type lateral diffused metal–oxide–semiconductor transistor (SJ-pLDMOS) utilizing electron to enhance the current capability is proposed. The proposed SJ-pLDMOS has an n-channel in the drain region and is controlled by an auto-generated voltage signal ( ${V}_{\mathrm {\textsf {Gn}}}$ ). The voltage signal ${V}_{\mathrm {\textsf {Gn}}}$ is generated during the ON- and OFF-state of the hole current which flows across an integrated resistor ( ${R}\text{p}$ ) implemented in the p-base region. Thus, the proposed SJ-pLDMOS utilizes both hole and electron currents to significantly enhance the current capability. Simulation results show that the current capability of the proposed SJ-pLDMOS without any conductivity modulation effect is comparable with that of a super-junction nLDMOS (SJ-nLDMOS). The total power loss of the proposed super-junction pLDMOS (SJ-pLDMOS) is reduced by about 26.7% and 18% compared with that of the SJ-nLDMOS and Triple Resurf nLDMOS (TR nLDMOS) at a rated load current density of $25~\mu \text{A}/\mu \text{m}$ , respectively.

Compact Modeling of Fin-LDMOS Transistor Based on the Surface Potential

One of the basic components of smart power integrated circuits (SPICs) is the laterally diffused metal oxide semiconductor (LDMOS) transistors. In this paper, we propose Fin-LDMOS transistor based on the surface potential. In order to improve the accuracy, we have taken into account not only the fin-shape structure of the gate but also the mobility reduction and saturation velocity. The proposed method is evaluated considering a broad range of biases and physical parameters of the device. The comparison between modeling results and 3D simulations confirm the remarkable accuracy of our model.

Nonlinear-Embedding Design Methodology Oriented to LDMOS Power Amplifiers

In this paper, we apply for the first time the nonlinear-embedding technique to the design of power amplifiers (PAs) based on laterally-diffused metal-oxide-semiconductor (LDMOS) field-effect transistors. Such a design technique is based on setting the transistor load line at the intrinsic current-generator plane, according to well-known theoretical guidelines. Then, the selected operating condition can be transposed at any design frequency at the extrinsic transistor terminals, by means of a model of the device nonidealities, such as the nonlinear intrinsic capacitances and the linear parasitic effects. A harmonically-tuned high-efficiency class-F and a wideband class-AB PAs operating within the FM broadcasting band 88 ÷ 108 MHz based on a 10-W LDMOS are then designed and realized. To definitely assess the validity of the proposed approach for the LDMOS technology, we compare the measured performance on the fabricated PAs with the expected predictions.