Simulation Study on the Optimization and Scaling Behavior of LDMOS Transistors for Low-Voltage Power Applications

Abstract

We present a systematic investigation of device optimization for laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistors in terms of subthreshold leakage current, breakdown voltage, and ON-resistance for low-voltage ( $10\boldsymbol {^{-13}}\text{A}/\boldsymbol {\mu }\text{m}$ while maintaining a breakdown voltage exceeding 10 V for channel lengths down to 10 nm. Interestingly, we find an optimal ON-resistance for a channel length of 40 nm, while for shorter channel lengths the ON-state resistance increases with decreasing channel length. The increasing resistance for shorter channels is caused by electron mobility degradation as a result of an increasing body doping, needed to limit the leakage current. The optimal channel length presents a limit to conventional scaling of LDMOS devices, commonly used in low-voltage power applications.