Laterally Diffused Metal Oxide Semiconductor Research Articles

Design of high reliability RF-LDMOS by suppressing the parasitic bipolar effect using enhanced p-well and double epitaxy**Project supported by the Chinese National Key Project (No. 2012ZX02502).

A laterally diffused metal–oxide–semiconductor (LDMOS) device design with an enhanced p-well and double p-epitaxial structure is investigated for device ruggedness improvement while keeping its high device performance under high frequency. Based upon the device design, radio-frequency (RF) LDMOS transistors for GSM (global system for mobile communication) application have been fabricated by using 0.35 μm CMOS technologies. Experimental data show that the proposed device achieves a breakdown voltage of 70 V, output power of 180 W. The RF linear gain is over 20 dB and the power added efficiency (PAE) is over 70% with the frequency of 920 MHz. In particular, it can pass the 20 : 1 voltage standing wave ratio (VSWR) load mismatch biased at drain DC supply voltage of 32 V and output power at 10-dB gain compression point (P10dB). The device ruggedness has been remarkably improved by using the proposed device structure.

A 100-V High-Performance SOI Trench LDMOS with Low Cell Pitch

In this paper, we report structural modifications in the conventional laterally diffused metal–oxide–semiconductor (LDMOS) field-effect transistor on thin silicon-on-insulator by incorporating trenches into the planar technology. The proposed power LDMOS includes two trenches built in the drift region on both sides of the p-base. The gate electrode is placed vertically in the left-side trench, while the right-side trench is filled with oxide. The proposed trench structure suppresses the electric field in the drift region due to the reduced-surface-field effect and allows increased doping concentration to achieve a better trade-off between breakdown voltage and on-resistance. At breakdown voltage of 103 V, the proposed device provides six times higher Baliga’s figure of merit, 38% decrease in gate–drain charge, and 9.5 times improvement in dynamic figure of merit as compared with the conventional LDMOS. Further, the proposed device achieves four times reduction in cell pitch as compared with the conventional structure.

GaN HEMT: Dominant Force in High-Frequency Solid-State Power Amplifiers

The gallium nitride (GaN) high-electron-mobility transistor (HEMT) has emerged as the dominant force in high-frequency solid-state power amplifiers (PAs)-not that it does not have competition. Silicon (Si) bipolar junction transistors (BJTs) and Si laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistors (FETs) are still commercially available. They are viable alternatives to GaN HEMTs in aerospace/defense applications such as L-band transponders/interrogators for the identification friend or foe; Link 16 data links; electronic warfare; and surveillance radar; and, in the case of Si LDMOSs, commercial cellular base stations. These older technologies can be favored due to their mature heritage, good performance, and low cost. The pseudomorphic HEMT (PHEMT) is ubiquitous in microwave and millimeter-wave power applications. Vacuum electron devices (VEDs) still reign in the regime of brute power. The GaN HEMT has been displacing these technologies as it has matured and costs have come down.

Numerical simulation of lateral diffused metal oxide semiconductor field effect transistors: A novel technique for electric field control to improve breakdown voltage

In this paper, we propose a novel technique to control the electric field in Lateral Diffused Metal Oxide Semiconductor (LDMOS) Field Effect Transistors, in order to increase the breakdown voltage. The key idea in this work is increasing the smoothness of the electric field by extra oxide (EO) on the gate sidewall at the drain side of a deep gate structure. The EO region effects on the breakdown voltage by uniformity of the electric field profile. Our results show that the electric field will be maximally flatted by optimization of EO region. Therefore, the proposed structure is called maximally flat deep gate LDMOS (MFDG-LDMOS). The novel features of MFDG-LDMOS are simulated and compared with a conventional LDMOS (C-LDMOS). Our results show that the breakdown voltage and the on-state resistance of the MFDG-LDMOS improve about 48% and 25% in comparison with the C-LDMOS, respectively.

Elimination of stress induced dislocation in deep Poly Sinker LDMOS technology

This work investigates the leakage current of power LDMOS (laterally diffused metal–oxide–semiconductor) transistors with deep poly sinker, and the leakage shows a certain wafer map distribution with most of the failed dies located at the center area. It is found that the leakage current is mainly caused by the stress-induced dislocations close to the deep poly sinker. The relationship between the stress-induced dislocation (SID) and the wafer warpage is studied. Experimental results show the dislocation and the resulting leakage current can be effectively eliminated, by either modifying the device layout or optimizing the fabrication process of the poly sinker.

Power performance of 65 nm CMOS integrated LDMOS transistors at WLAN and X-band frequencies

Laterally diffused metal oxide semiconductor (LDMOS) transistors with 10 V breakdown voltage have been implemented in a 65 nm Complementary metal oxide semiconductor (CMOS) process without extra masks or process steps. Radio frequency (RF) performance for Wireless local area network (WLAN) frequencies and in X-band at 8 GHz is investigated by load-pull measurements in class AB operation for both 3.3 and 5 V supply voltage. Results at 2.45 GHz showed 290 mW/mm output power density with 17 dB linear gain and over 45% power added efficiency (PAE) at 4 dB compression at a supply voltage of 5 V. Furthermore, results in X-band at 8 GHz show 8 dB linear gain, 320 mW/mm output power density and over 22% PAE at 4 dB compression. Third-order intermodulation measurements at 8 GHz revealed OIP3 of 18.9 and 21.9 dBm at 3.3 and 5 V, respectively. The transistors were also tested for reliability which showed no drift in quiescent current after 26 h of DC stress while high-power RF stress showed only small extrapolated drift at 10 years in output power density. This is to the authors' knowledge the first time high output power density in X-band is demonstrated for integrated LDMOS transistors manufactured in a 65 nm CMOS process without extra process steps.

Doherty Power Amplifier with Dynamic Power Dividing Network for Enhanced Efficiency

In this paper, we present a high efficiency Doherty power amplifier (PA) employing dynamic power dividing network which automatically adjusts the input power division ratio in accordance with the level of input power to enhance efficiency. Doherty PA circuit parameters of each amplifier are determined by basic performance analysis according to the datasheet. Simulated circuits through Advanced Design System (ADS) exhibit an improvement of 4% at a 6 dB backoff point from its saturated output power (PSAT) than that of a conventional Doherty PA. Implemented Doherty PA using two Freescale MRF6S27015N laterally diffused metal oxide semiconductor (LDMOS) field-effect transistors (FETs) achieves excellent drain efficiency of 46.5% at a 6 dB backoff point from PSAT, which is 2% higher than conventional Doherty PA.

Thin layer oxide in the drift region of Laterally double-diffused metal oxide semiconductor on silicon-on-insulator: A novel device structure enabling reliable high-temperature power transistors

In this paper a new lateral double diffused metal oxide semiconductor (LDMOS) transistor on silicon-on-insulator (SOI) technology is reported. In the proposed structure a trench oxide in the drift region is reformed to reduce surface temperature. In the LDMOS devices one way for achieving high breakdown voltage is incorporating the trench oxide in the drift region. But, this strategy causes high lattice temperature in the device. So, the middle of the trench oxide in the drift region is etched and filled with the silicon to have higher thermal conductivity material and reduce the lattice temperature in the drift region. The simulation with two-dimensional ATLAS simulator shows that the novel thin trench oxide in the n-drift region of LDMOS transistor (TT-LDMOS) have lower maximum lattice temperature with an acceptable breakdown voltage in respect to the conventional LDMOS (C-LDMOS) structure with the trench oxide in the drift region. So, TT-LDMOS can be a reliable device for power transistors.

Two‐stage hot‐carrier‐induced degradation of p‐type LDMOS transistors

Hot-carrier-induced device degradation of high-voltage p-type lateral diffused metal–oxide semiconductor (LDMOS) transistors is investigated. A two-stage linear region drain current (IDlin) shift (IDlin shift increases rapidly at the beginning of stress but tends to saturate when the stress time is longer) is observed. Technology computer-aided-design simulations and direct current current–voltage measurement results suggest that the decrease of residual fabrication interface traps (NIT) leads to an initial increase in IDlin shift. On the other hand, two competing mechanisms, i.e. increase in NIT generation and increase in electron trapping, are responsible for the saturated IDlin shift when the stress time is longer.

Investigation of the trigger voltage walk-in effect in LDMOS for high-voltage ESD protection

The trigger voltage walk-in effect has been investigated by designing two different laterally diffused metal—oxide—semiconductor (LDMOS) transistors with an embedded silicon controlled rectifier (SCR). By inserting a P+ implant region along the outer and the inner boundary of the N+ region at the drain side of a conventional LDMOS transistor, we fabricate the LDMOS-SCR and the SCR-LDMOS devices with a different triggering order in a 0.5 μm bipolar-CMOS-DMOS process, respectively. First, we perform transmission line pulse (TLP) and DC-voltage degradation tests on the LDMOS-SCR. Results show that the trigger voltage walk-in effect can be attributed to the gate oxide trap generation and charge trapping. Then, we perform TLP tests on the SCR-LDMOS. Results indicate that the trigger voltage walk-in effect is remarkably reduced. In the SCR-LDMOS, the embedded SCR is triggered earlier than the LDMOS, and the ESD current is mainly discharged by the parasitic SCR structure. The electric potential between the drain and the gate decreases significantly after snapback, leading to decreased impact ionization rates and thus reduced trap generation and charge trapping. Finally, the above explanation of the different trigger voltage walk-in behavior in LDMOS-SCR and SCR-LDMOS devices is confirmed by TCAD simulation.

Performance drifts of N-MOSFETs under pulsed RF life test

This paper presents a reliability life test bench specifically dedicated to high RF power devices for lifetime tests under pulse conditions. The monitoring of RF power, drain, gate voltages and currents under various pulses and temperatures conditions are investigated. A 3000h pulsed RF life test has been conducted on a dedicated RF S-band test bench in operating modes. The investigation findings of degradations of critical electrical parameters derived from the data treatment after this accelerated ageing tests are presented. Numerous duty cycles are applied in order to stress Lateral-Diffused Metal-Oxide-Semiconductor (LDMOS). It shows with tracking of a set of RF parameters (Pout, Gain and Drain Efficiency: DE) that the dominant degradation phenomenon is linked to hot carriers generated interface states (traps) and trapped electrons. Which results in a build up of negative charge at Si/SiO2 interface and the main cause appear with incidence on RF power device. Physical simulation software (Silvaco-Atlas) has been used to locate and confirm these phenomena.

MMIC-based asymmetric Doherty power amplifier for small cells applications

We present the results obtained on a multi-mode multi-band 20 W Monolithic Microwave Integrated Circuit (MMIC) power amplifier. The proposed two-stage circuit is based on the silicon Laterally Diffused Metal Oxide Semiconductor (LDMOS) technology. Thanks to dedicated design techniques, it can cover the Digital Cellular Service (DCS), Personal Communications Service (PCS), and UMTS bands (ranging from 1.805 to 2.17 GHz) and deliver more than 20 W of output power, 30 dB of gain and 50% of power added efficiency. When combined in a Doherty configuration with an incremental 40 W MMIC in a dual-path package, the resulted asymmetric MMIC (an industry first) can deliver an unprecedented LDMOS MMIC efficiency of up to 44% at 8 dB back-off in the UMTS band. Then, the DPA has been optimized in conjunction with a novel RF pre-distortion technique, leading to 33–80% energy saving at the system level.

High temperature behavior of multi-region direct current current–voltage spectroscopy and relationship with shallow-trench-isolation-based high-voltage laterally diffused metal–oxide–semiconductor field-effect-transistors reliability

With the process compatibility with the mainstream standard complementary metal–oxide–semiconductor (CMOS), shallow trench isolation (STI) based laterally diffused metal–oxide–semiconductor (LDMOS) devices have become popular for its better tradeoff between breakdown voltage and performance, especially for smart power applications. A multi-region direct current current–voltage (MR-DCIV) technique with spectroscopic features was demonstrated to map the interface state generation in the channel, accumulation and STI drift regions. High temperature behavior of MR-DCIV spectroscopy was analyzed and a physical model was verified. Degradation of STI-based LDMOS transistors under high temperature reverse bias (HTRB) stress is experimentally studied by MR-DCIV spectroscopy. The impact of interface state location on device electrical characteristics was investigated. Our results show that the major contribution to HTRB degradation, in term of the on-resistance degradation, was attributed to interface state generation under STI drift region.

A low on-resistance silicon on insulator lateral double diffused metal oxide semiconductor device with a vertical drain field plate

To reduce the on-resistance and enhance the breakdown voltage of silicon on insulator (SOI) lateral double diffused metal oxide semiconductor (LDMOS) device at the same time, a low on-resistance SOI-LDMOS device with a vertical drain field plate and trench gate and trench drain (VFP-TGTD-SOI-LDMOS) is proposed. The device has the features as follows: first, a trench gate and a trench drain are adopted, which can widen the vertical current conduction area, shorten the lateral current conduction path, and lower the on-resistance. Secondly, a vertical field plate is used, which modulates the electric field around it, reduces the high electric field at the end of the drain electrode, and increases the breakdown voltage. The VFP-TGTD-SOI device is compared with a conventional SOI device, a trench gate SOI device, a trench gate and trench drain SOI device with the same dimensional device parameters using the two-dimensional semiconductor simulator MEDICI. The results show that under the condition of their own highest figure of merit (FOM), the specific on-resistance value of the VFP-TGTD-SOI device is reduced by 53%, 23%, and increased by 87%, respectively and the breakdown voltage is increased by 4% and reduced by 9% and increased by 45%, respectively. By comparing the FOMs of the four structures, it can be seen that the VFP-TGTD-SOI device has the highest FOM, which indicates that among the four structures, it maintains the lower on-resistance and holds the higher breakdown voltage at the same time.

Power amplifier linearisation scheme to mitigate superfluous radiations and suppress adjacent channel interference

Power amplifiers are one of the costly devices in wireless communication systems and exhibit non-linearity. The problem of non-linearity in the power amplifier categorises in two disturbance impacts, output distortion and in-band distortion which lead to adjacent channel interference and constellation deviation, respectively. In order to gain maximum efficiency of the power amplifier and reduce interference, the authors propose a new digital pre-distortion scheme called complex gain convergence (CGC). The proposed scheme is compared with indirect learning architecture and validated against an laterally diffused metal oxide semiconductor (LDMOS) power amplifier. The outcome of applying CGC scheme shows enhancement in adjacent channel leakage ratio and error vector magnitude performance while the complexity is even lower. An experimental demonstration with the actual power amplifier is also presented.

Nonlinear modeling of LDMOS transistors for high‐power FM transmitters

SUMMARYIn this paper, a nonlinear model of a commercial 10‐W laterally diffused metal oxide semiconductor (LDMOS) transistor for FM transmitters is identified. It is based on high‐frequency small‐signal measurements for the identification of both the parasitic network and the strictly nonlinear dynamic effects, whereas low‐frequency large‐signal measurements are exploited for the description of the dynamic I/V characteristics of the device above the cut‐off of low‐frequency dispersion. A validation of the proposed model is provided by using time‐domain nonlinear measurements carried out at 40 MHz and 100 MHz. Copyright © 2013 John Wiley & Sons, Ltd.

A 700-V Device in High-Voltage Power ICs With Low On-State Resistance and Enhanced SOA

This paper presents a 700-V high-voltage laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistor with a p-body_Extension reduce surface field (RESURF) structure. Experimental results demonstrate that the low ON resistance and breakdown voltage (BV)- RON,sp figure of merit approach the ideal Baliga's power law, in addition, breaks the quasi-saturation limitation with enhanced device safe operating area (SOA). The optimal charge balance and geometrical design to achieve the lowest specific ON resistance (RON,sp) with the desired maximum high BV are displayed and discussed by simulations and experimental results. The 2-D simulations confirmed that, compared with conventional triple-RESURF structures, the presented device provides a fourfold reduction in the surface electric field on the source side and a 32% improvement in blocking voltage. The specific ON resistance demonstrates superior 40% lower performance than published Junction Isolation LDMOS device families. In addition, its twofold increase in SOA extension can improve the performance of circuit designs for switching power supply applications.

Performance Improvement in RF LDMOS Transistors Using Wider Drain Contact

In this letter, we proposed a new layout structure for RF laterally diffused metal-oxide-semiconductor (LDMOS) transistors. In a multifinger layout, the drain contact region was designed to be wider than the channel region. The wider drain increases the equivalent drift region width to reduce the drift resistance and suppress the quasi-saturation effect. We found that the wide-drain multifinger LDMOS devices have lower on-resistance, higher cutoff frequency, higher maximum oscillation frequency, and better power performances than the standard multifinger ones.

A novel high voltage lateral double diffused metal oxide semiconductor (LDMOS) device with a U-shaped buried oxide feature

A novel U-shape buried oxide lateral double diffused metal oxide semiconductor (LDMOS) is reported in this paper. The proposed structure features ionized charges in both sides of dielectric between source and gate region to enhance the breakdown voltage. The dielectric between drain and drift region affects on the breakdown voltage by adding a new peak in the electric field profile. Two dimensional simulation with a commercial software tool predicts significantly improved performance of the proposed device as compared to conventional LDMOS structures.

Lead zirconate titanate behaviors in an LDMOS

The behaviors of lead zirconate titanate (PZT) deposited as the dielectric for high-voltage devices are investigated experimentally and theoretically. The devices demonstrate not only high breakdown voltages above 350 V, but also excellent memory behaviors. A drain current—gate voltage (ID—VG) memory window of about 2.2 V is obtained at the sweep voltages of ±10 V for the 350-V laterally diffused metal oxide semiconductor (LDMOS). The retention time of about 270 s is recorded for the LDMOS through a controlled ID—VG measurement. The LDMOS with memory behaviors has potential to be applied in future power conversion circuits to boost the performance of the energy conversion system.