Latch Design Research Articles

Non-Volatile Spintronic Flip-Flop Design for Energy-Efficient SEU and DNU Resilience

In this paper, low-energy radiation-hardening approaches are proposed to develop non-volatile (NV) flip-flop (FF) circuits using spintronic devices. In particular, spin Hall effect magnetic tunnel junctions are used to design a radiation-hardened NV-latch that is proposed to be utilized as a shadow latch to maintain the data during the standby mode when the circuit is power-gated. Moreover, soft-error resilient complementary metal–oxide–semiconductor-based latching circuits are designed to be leveraged as master and slave latches in the NVFF structure. The proposed hardening techniques are based on using feedback loops and clock-gating Muller C-elements, as well as increasing the charge capacity of the vulnerable nodes. The circuit simulations indicate that the proposed single-event upset and double node upset resilient latching circuits can achieve at least 81% and 24% power-delay product improvement, respectively, while incurring comparable area overhead compared to the previous energy-efficient radiation-hardened latch designs. Finally, the proposed latching circuits are combined to develop four radiation-hardened NVFF designs. The results obtained show that, using the proposed NV latching circuit as a shadow latch can result in two orders of magnitude reduction in energy consumption compared to the FF circuits with an NV master latch. In addition, the proposed latches achieve favorable tradeoffs in terms of minimized performance overheads and maximized robustness (100%) of soft fault coverage to single and double upsets. Thus, the proposed NVFFs can be employed within logic datapaths to ensure data integrity as a potential mainstream solution for aerospace and avionic nanoelectronics.

A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application

This brief presents a double-node upset (DNU) self-recoverable latch design for high performance and low power application. The latch is mainly constructed from eight mutually feeding back C-elements and any node pair of the latch is DNU self-recoverable. Using a high speed transmission path and a clock gating technique, the latch has high performance and low power dissipation. Simulation results demonstrate the DNU self-recoverability of the latch and also show that the delay-power-area product of the latch is improved approximately by 81.80% on average, compared with the latest DNU self-recoverable latch designs.

High robust and cost effective double node upset tolerant latch design for nanoscale CMOS technology

In this paper, we propose a novel high reliability and low cost DNU (Double Node Upset) tolerant latch, HRCE (High Robust and Cost Effective) latch, for nanoscale CMOS technology. In the presence of the interlocked feedback loop composed of C-elements and inverters, the proposed latch design can self-recover from the DNU. The proposed latch is evaluated and compared to previous soft error (SE) tolerant latches, and SPICE simulations are carried out with SMIC 65 nm technology model. Simulation results indicated that our proposed latch saves approximately 84.5% APDP (Area-Power-Delay Product) on average with the lowest APDP. Besides, we investigated the PVT (process, voltage and temperature) variations effects on the HRCE latch and other hardened latches, and the results indicated that the HRCE latch has less sensitivity towards process variation.

Using MRED to Screen Multiple-Node Charge-Collection Mitigated SOI Layouts

Silicon-on-insulator latch designs and layouts that are robust to multiple-node charge collection are introduced. A general Monte Carlo radiative energy deposition (MRED) approach is used to identify potential single-event susceptibilities associated with different layouts prior to fabrication. MRED is also applied to bound single-event testing responses of standard and dual interlocked cell latch designs. Heavy ion single-event testing results validate new latch designs and demonstrate bounds for standard latch layouts.

A single event upset tolerant latch design

This paper presents a single-event-upset tolerant latch design based on a redundant structure featuring four storage nodes (i.e. Quatro). The reference structure manifests single node upset issues when either of the two internal nodes is hit and observes a positive transient afterwards. Two OFF-state transistors are added to those two internal pull-up paths, suppressing positive transient. Simulation and experimental data demonstrate that the proposed design has smaller cross section and higher upset threshold than the reference design.

TiC-composite materials in applications for kinematic denture connections

PurposeThis paper presents an own proposal for the construction of a ball latch intended for use in prosthetic dentistry. Attention was paid to the existing commercial constructions of elements of the same type, indicating their advantages and disadvantages. Based on the analysis of the present solutions, own ones were proposed. Materials and methodsThe following materials were chosen for the tests: pure titanium, 316 L V steel, Ti15Mo2.8Nb obtained using powder metallurgy and through mechanical alloying, 10 and 20% of titanium carbide – obtained using powder metallurgy, as well as 10 and 20% of graphite – obtained using powder metallurgy. For the prepared materials, tribological tests were performed using a friction simulator in a ring/shield system. ResultsFairly extensive tests were performed to verify the suitability of the selected material for use in the specific conditions of the oral cavity. The performed tests showed that the proposed material is not only beneficial in relation to the existing commercial dental alloys but also meets the general criteria set for this type of elements. ConclusionsA more beneficial use of two–part ball latches (two key parts – patrix, matrix) was noticed in comparison to latches consisting of three parts (patrix, insert, matrix). On the basis of the obtained test results, it can be concluded that the proposed own design of a ball latch is a good alternative for traditional constructional and material solutions of commercial ball latches.

An Inkjet-Printed Low-Voltage Latch Based on Inorganic Electrolyte-Gated Transistors

Printed electronics is a fast-growing emerging technology, which is expected to play a major role in smart sensors for the Internet of Things domain. While there has been considerable progress at the device level by new materials, on circuit level results are still rare. In this letter, we report on the design, simulation, fabrication, and measurement of an inkjet-printed latch, which is an essential building block for digital circuits. Our technology approach is based on electrolyte-gated transistors, which enables low-voltage operation and yields an outstanding electrical performance due to high mobility of the semiconducting, precursor-made In2O3 channel. The fabricated latch can operate reliably down to 0.6 V, where the power consumption is only 16 $\mu \text{W}$ . The area requirement is about 7 mm2, and in terms of lifetime, no performance degradation was observed during an experimental period of 12 weeks.

Low‐cost single event double‐upset tolerant latch design

This Letter proposes a low-cost, single event double-upset tolerant latch which utilises interlocked nodes to keep data, clock gating (CG) in Muller C-element (MCE) to turn off the storage cell, a three-input MCE to block the soft error from the storage cell and a weak keeper to prevent high impedance state. The storage cell in the proposed latch has better reliability than the conventional triple path dual-interlocked storage cell (TPDICE). Most up-to-date single event double-upset (SEDU) tolerant latches are carried out with too large cost penalties. The proposed one saves up to 93.32% area-power-delay product (APDP) compared with one up-to-date SEDU tolerant latch and even saves 36.36% APDP compared with only single event upset (SEU) tolerant latch in the referential. Simulation results have verified SEU and SEDU tolerance of the proposed latch.

Quantification of the likelihood of single event multiple transients in logic circuits in bulk CMOS technology

It is well known that high-energy particle strikes on an integrated circuit can cause circuit errors. We quantify the fraction of a layout which is susceptible to multiple transients, through the notion of critical area fraction (CAF). We perform a 2D-study on a layout of 65 nm planar transistors to evaluate maximum values of CAF. We find that CAF can be as high as 1, that is, 100% of the layout area is vulnerable. Potentials of adjacent source/drain regions play a significant role in increasing the CAF and simple layout techniques do not reduce the CAF substantially. We confirm these observations through 3D simulations of inverter layouts. A key observation is that, CAF is high in the region of the layout which contains small gates. At the circuit-level, multiple transients not only cause multiple errors, they also merge to create wider transient increasing its capture probability. A circuit-aware placement of vulnerable gates and alternate latch designs may be required to alleviate the problem.

Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology

This brief presents a double-node-upset-resilient latch (DNURL) design in 22-nm CMOS technology. The latch comprises three interlocked single-node-upset-resilient cells and each of the cells mainly consists of three mutually feeding back Muller C-elements. Simulation results demonstrate the double-node upset resilience and a 73.0% delay-power-area product saving on average compared with the up-to-date DNURL designs.

Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops

With technology down scaling, static power has become one of the biggest challenges in a system on chip . Normally off computing using nonvolatile (NV) sequential elements is a promising solution to address this challenge. Recently, many NV shadow flip-flop architectures have been introduced in which magnetic tunnel junction (MTJ) cells are employed as backup storing elements. Due to the emerging fabrication processes of magnetic layers, MTJs are more susceptible to manufacturing defects than their CMOS counterparts. Moreover, unlike memory arrays that can effectively be repaired with well-established memory repair and coding schemes, flip-flops scattered in the layout are more difficult to repair. Therefore, without effective defect and fault tolerance for NV flip-flops, the manufacturing yield will be affected severely. In this paper, we propose a fault-tolerant NV latch (FTNV-L) design, in which several MTJ cells are arranged in such a way that it is resilient to various MTJ faults. The simulation results show that our proposed FTNV-L can effectively tolerate all single MTJ faults with a considerably lower overhead than traditional approaches.

Design of QCA Latch Using Three Dimensional Loop Structure

Design of QCA Latch Using Three Dimensional Loop Structure

Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS

Technology scaling results in that, single event effects, such as single event double-upset due to double-node charge sharing, and single event transient (i.e. an invalid pulse) propagated from upstream combinational blocks, are becoming increasingly serious with technology evolution. In this paper, a single event double-upset fully immune and single event transient filterable latch is proposed in 65nm CMOS technology. By means of a triple-input Muller C-element, which is driven through a clock gating based triple path DICE, all internal nodes and output node of the latch not only self-recover from single event upset regardless of the energy of a striking particle, but also tolerate single event double-upset when any arbitrary combination of the node pairs is affected. Further, taking advantage of a keeper connected to the output node, the latch is insensitive to a high impedance state. Besides, making use of an embedded Schmitt trigger inverter on the propagation path, the latch also effectively filters single event transient. Simulation results have demonstrated the single event double-upset fully immunity, single event transient filterability, and cost effectiveness, i.e. approximate 60.41% area-power-delay product saving for the latch, compared with the single event double-upset fully immune DNCS-SEI latch, which cannot filter single event transient at all.

Charge-Steering Latch Design in 16 nm FinFET Technology for Improved Soft Error Hardness

A charge-steering based latch hardening technique with very low performance tradeoff and significant SEU hardness is presented. Mixed-mode 3D-TCAD simulations are used to illustrate the effect of charge steering in reducing the amount of collected charge at the critical sensitive nodes. Circuit simulations also highlight that the tradeoffs in terms of area, speed and power penalties are much lower compared to other hardening approaches, such as hysteresis and spatial-redundancy techniques. Alpha particle, heavy-ion, and proton test results for circuits designed in a 16 nm FinFET process indicate significant SEU hardness, comparable to DICE FF design, for low LET particles.

An Area Efficient Stacked Latch Design Tolerant to SEU in 28 nm FDSOI Technology

In this paper, we present D flip-flop, Quatro, and stacked Quarto flip-flop designs fabricated in a commercial 28-nm CMOS FDSOI technology. Stacked-transistor structures are introduced in the stacked Quatro design to protect the sensitive devices of the original structure. Striking either of the stacked devices will not upset the latch because the conduction path to the supply rail is still cut off by the other off-state device. The irradiation experimental results substantiate that the stacked Quatro design has significantly better SEU tolerance (e.g., higher heavy ion upset Linear Energy Transfer threshold and smaller cross-section data) than the reference designs. It introduces power and area penalties because the proposed design duplicates and stacks two sensitive PMOS devices. Additionally, the impact of technology scaling on Quatro in various technology nodes (130-nm, 65-nm, and 40-nm) has been studied suggesting decreasing upset threshold and decreasing cross-section data.

High‐performance, low‐cost, and highly reliable radiation hardened latch design

Technology scaling results in that, soft errors, due to radiation-induced single event double-upset (SEDU) that affects double nodes through charge sharing, become a prominent concern in nanoscale CMOS technology. Existing hardened schemes suffer from being not fully SEDU-immune, or perform with too large cost penalties regarding propagation delay, silicon area, and power dissipation. A novel high-performance, low-cost, and fully SEDU-immune latch, referred to as HSMUF, is presented to tolerate SEDU when any arbitrary combination pair of nodes is affected by a particle striking. The latch mainly consists of a clock gating-based triple path DICE and a multiple-input Muller C-element. Simulation results demonstrate the SEDU-immunity and a 99.73% area–power–delay product saving for the HSMUF latch, compared with the SEDU fully immune DNCS-SEUT latch.

Analysis and Reduction of Power in all Digital PLL Architecture by using Dynamic PFD with CWSP

Dynamic Phase Frequency Detector with CWSP, Mainly focusing on reducing power consumption, and fast-locking ability and has been used to reduce the delay moments Demonstrated 0.25μm CMOS technology. DTC needed assistance through a phase prediction means substantial energy savings and thus reduces range. A Low power all digital phase Locked Loop (PLL), they have become very attractive because good on a variety of actions, programmability, stability, portability, testability and yield and is better ADPLL Immunogenic noise. The key is to measure the time difference between time-to-digital converter Rising edges of signals. Time-to-digital converter (TDC) ADPLL integrated within. DTC delay Divided reference clock and the feedback clock is like the chain latch design is a comparison between the phase error Low power consumption. The complete ADPLL system improves the performance of the locking ability and the system DTC linearity. The design is implemented using DPFD with CWSP technique was more suitable for high speed phase frequency detector. The proposed system of dynamic phase frequency detector with CWSP has been fabricated and the corresponding power consumed is 75 μW.

Low power and high write speed SEU tolerant SRAM data cell design

As feature size scales down, reliability issues like single event upset (SEU) have become serious for circuit and system designers, especially for those who work on memory and latch designs. In this paper, an improved SEU tolerant data cell design based on the Quatro-10T cell is proposed. The introduced cell enhances the capability of SEU tolerance by weakening the key transistors in the feedback loop to block the effects of transient fault. Simulation results show that our proposed design achieves obvious higher resilience to SEU and better performance on speed and power dissipation at the expense of an increased area. The proposed cell is a fully SEU immune design with an amount of critical charge at least 7 times more than the Quatro-10T cell and has the lowest Power Delay Product. It shows that our design is very suitable in high-performance circuit and system design.

Design and Implementation of Adiabatic Latch for Low Power Embedded Systems

Design and Implementation of Adiabatic Latch for Low Power Embedded Systems

Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology

As a consequence of technology scaling down, gate capacitances and stored charge in sensitive nodes are decreasing rapidly, which makes CMOS circuits more vulnerable to radiation induced soft errors. In this paper, a low cost and highly reliable radiation hardened latch is proposed using 65nm CMOS commercial technology. The proposed latch can fully tolerate the single event upset (SEU) when particles strike on any one of its single node. Furthermore, it can efficiently mask the input single event transient (SET). A set of HSPICE post-layout simulations are done to evaluate the proposed latch circuit and previous latch circuits designed in the literatures, and the comparison results among the latches of type 4 show that the proposed latch reduces at least 39% power consumption and 67.6% power delay product. Moreover, the proposed latch has a second lowest area overhead and a comparable ability of the single event multiple upsets (SEMUs) tolerance among the latches of type 4. Finally, the impacts of process, supply voltage and temperature variations on our proposed latch and previous latches are investigated.