High robust and cost effective double node upset tolerant latch design for nanoscale CMOS technology

Abstract

In this paper, we propose a novel high reliability and low cost DNU (Double Node Upset) tolerant latch, HRCE (High Robust and Cost Effective) latch, for nanoscale CMOS technology. In the presence of the interlocked feedback loop composed of C-elements and inverters, the proposed latch design can self-recover from the DNU. The proposed latch is evaluated and compared to previous soft error (SE) tolerant latches, and SPICE simulations are carried out with SMIC 65 nm technology model. Simulation results indicated that our proposed latch saves approximately 84.5% APDP (Area-Power-Delay Product) on average with the lowest APDP. Besides, we investigated the PVT (process, voltage and temperature) variations effects on the HRCE latch and other hardened latches, and the results indicated that the HRCE latch has less sensitivity towards process variation.