Non-Volatile Spintronic Flip-Flop Design for Energy-Efficient SEU and DNU Resilience

Abstract

In this paper, low-energy radiation-hardening approaches are proposed to develop non-volatile (NV) flip-flop (FF) circuits using spintronic devices. In particular, spin Hall effect magnetic tunnel junctions are used to design a radiation-hardened NV-latch that is proposed to be utilized as a shadow latch to maintain the data during the standby mode when the circuit is power-gated. Moreover, soft-error resilient complementary metal–oxide–semiconductor-based latching circuits are designed to be leveraged as master and slave latches in the NVFF structure. The proposed hardening techniques are based on using feedback loops and clock-gating Muller C-elements, as well as increasing the charge capacity of the vulnerable nodes. The circuit simulations indicate that the proposed single-event upset and double node upset resilient latching circuits can achieve at least 81% and 24% power-delay product improvement, respectively, while incurring comparable area overhead compared to the previous energy-efficient radiation-hardened latch designs. Finally, the proposed latching circuits are combined to develop four radiation-hardened NVFF designs. The results obtained show that, using the proposed NV latching circuit as a shadow latch can result in two orders of magnitude reduction in energy consumption compared to the FF circuits with an NV master latch. In addition, the proposed latches achieve favorable tradeoffs in terms of minimized performance overheads and maximized robustness (100%) of soft fault coverage to single and double upsets. Thus, the proposed NVFFs can be employed within logic datapaths to ensure data integrity as a potential mainstream solution for aerospace and avionic nanoelectronics.