Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes

Abstract

In this paper, an ultralow-power true single-phase clocking flip-flop (FF) design achieved using only 19 transistors is proposed. The design follows a master–slave-type logic structure and features a hybrid logic design comprising both static-CMOS logic and complementary pass-transistor logic. In the design, a logic structure reduction scheme is employed to reduce the number of transistors for achieving high power and delay performance. Despite its circuit simplicity, no internal nodes are left floating during the operation to avoid leakage power consumption. In this design, a virtual $V_{{\mathrm{DD}}}$ design technique, which facilitates a faster state transition in the slave latch, is devised to enhance time performance. In circuit implementation, transistor sizes are optimized with respect to the power-delay product (PDP). A TSMC 90-nm CMOS process was selected as the implementation technology. In this paper, the performance levels of seven FF designs were compared. The timing parameters of each FF were first characterized. Post-layout simulation results indicated that the proposed design excelled in various performance indices such as PDP, clock-to-Q delay, average power consumption, and leakage power consumption. Moreover, the design was determined to have the smallest layout area. Compared with the conventional transmission-gate-based FF design, the PDP improvement in the proposed design was up to 63.5% (at 12.5% switching activity) and the area saving was approximately 10%. Further simulations on process corners, supply voltage settings, and working frequencies were conducted to study the design reliability.