Low power and high write speed SEU tolerant SRAM data cell design

Abstract

As feature size scales down, reliability issues like single event upset (SEU) have become serious for circuit and system designers, especially for those who work on memory and latch designs. In this paper, an improved SEU tolerant data cell design based on the Quatro-10T cell is proposed. The introduced cell enhances the capability of SEU tolerance by weakening the key transistors in the feedback loop to block the effects of transient fault. Simulation results show that our proposed design achieves obvious higher resilience to SEU and better performance on speed and power dissipation at the expense of an increased area. The proposed cell is a fully SEU immune design with an amount of critical charge at least 7 times more than the Quatro-10T cell and has the lowest Power Delay Product. It shows that our design is very suitable in high-performance circuit and system design.